Method and circuit for testing memories in integrated circuit form

Claim 2

An integrated circuit memory, comprising: an array of memory cells arranged in rows and columns; one or more precharging and reading subcircuits, each operatively connected to at least one respective column of said array of memory cells, and each comprising: a current-to-voltage converter having an input terminal connected to be driven by a current signal from said respective column, and having an output terminal connected to provide a voltage signal corresponding to said current signal, a precharging circuit connected to selectably drive said voltage signal toward a power supply voltage, a read circuit connected to detect the voltage of said voltage signal and provide a corresponding digital output, a first bypass transistor connected to selectably bypass said read circuit, but not said current-to-voltage converter, under control of a first test-mode control signal; and an output terminal operatively connected to said digital output; wherein said precharging circuit is controlled in dependence both on a clock signal and also on a second test-mode control signal.

Claim 3

The integrated circuit of claim 1, wherein said array of memory cells consists of an array of floating-gate memory cells.

Claim 4

The integrated circuit of claim 1, wherein each said precharging/reading subcircuit is connected to a plurality of column-select transistors which are each connected to a respective column of said array of memory cells.

Claim 5

The integrated circuit of claim 1, wherein said first bypass transistor is an n-channel field-effect transistor.

Claim 6

The integrated circuit of claim 1, wherein said current-to-voltage converter comprises an n-channel field-effect series transistor interposed between said precharging circuit and said input terminal; and logic circuitry connected to drive a gate of said series transistor with a signal which varies inversely with the voltage of said input terminal.

Claim 7

An integrated circuit, comprising: an array of memory cells arranged in rows and columns; one or more precharging and reading subcircuits, each operatively connected to at least one respective column of said array of memory cells, and each comprising: a current-to-voltage converter having an input terminal connected to be driven by a current signal from said respective column, and having an output terminal connected to provide a voltage signal corresponding to said current signal when an enable signal is active, a precharging circuit connected to selectably drive said voltage signal toward a power supply voltage, a read circuit connected to detect the voltage of said voltage signal and provide a corresponding digital output through an output register, a first bypass transistor connected to selectably bypass said read circuit and said output register, but not said current-to-voltage converter, under control of a first test-mode control signal; and an output terminal operatively connected to said digital output; wherein said precharging circuit is controlled in dependence both on a clock signal and also on a second test-mode control signal.

Claim 8

An integrated circuit, comprising: an array of memory cells arranged in rows and columns; one or more precharging and reading subcircuits, each operatively connected to at least one respective column of said array of memory cells, and each comprising: a current-to-voltage converter having an input terminal connected to be driven by a current signal from said respective column, and having an output terminal connected to provide a voltage signal corresponding to said current signal when an enable signal is active, a precharging circuit connected to selectably drive said voltage signal toward a power supply voltage, a read circuit connected to detect the voltage of said voltage signal and provide a corresponding digital output through an output register, a first bypass transistor connected to selectably bypass said read circuit and said output register, but not said current-to-voltage converter, under control of a first test-mode control signal; and an output terminal operatively connected to said digital output; wherein said precharging circuit is controlled in dependence both on a clock signal and also on a second test-mode control signal.

Claim 9

The integrated circuit of claim 6, wherein said array of memory cells consists of an array of floating-gate memory cells.

Claim 10

The integrated circuit of claim 6, wherein each said precharging/reading subcircuit is connected to a plurality of column-select transistors which are each connected to a respective column of said array of memory cells.

Claim 11

The integrated circuit of claim 6, wherein said first bypass transistor is an n-channel field-effect transistor.

Claim 12

The integrated circuit of claim 6, wherein said current-to-voltage converter comprises an n-channel field-effect series transistor interposed between said precharging circuit and said input terminal; and logic circuitry connected to drive a gate of said series transistor with a signal which varies inversely with the voltage of said input terminal.

Claim 13

An integrated circuit memory, comprising: an array of memory cells; and one or more precharging and reading subcircuits, each selectably connected to multiple respective multi-cell portions of said array of memory cells, and each comprising: an impedance element having an input terminal connected to be driven by said respective portion of said array, and having an output terminal connected to provide a voltage signal which indicates signals received at said input terminal; a precharging circuit connected to selectably drive said voltage signal toward a power supply voltage, a read circuit connected to detect the voltage of said voltage signal and provide a corresponding digital output, a first bypass transistor connected to selectably bypass said read circuit, but not said impedance element, under control of a first test-mode control signal; and an output terminal operatively connected to said digital output; wherein said precharging circuit is controlled in dependence both on a clock signal and also on a second test-mode control signal.

Claim 14

An integrated circuit memory, comprising: an array of memory cells; and one or more precharging and reading subcircuits, each selectably connected to multiple respective multi-cell portions of said array of memory cells, and each comprising: an impedance element having an input terminal connected to be driven by said respective portion of said array, and having an output terminal connected to provide a voltage signal which indicates signals received at said input terminal; a precharging circuit connected to selectably drive said voltage signal toward a power supply voltage, a read circuit connected to detect the voltage of said voltage signal and provide a corresponding digital output, a first bypass transistor connected to selectably bypass said read circuit, but not said impedance element, under control of a first test-mode control signal; and an output terminal operatively connected to said digital output; wherein said precharging circuit is controlled in dependence both on a clock signal and also on a second test-mode control signal.

Claim 15

The integrated circuit of claim 11, wherein said array of memory cells consists of an array of floating-gate memory cells.

Claim 16

The integrated circuit of claim 11, wherein each said precharging/reading subcircuit is connected to a plurality of column-select transistors which are each connected to a respective column of said array of memory cells.

Claim 17

The integrated circuit of claim 11, wherein said first bypass transistor is an n-channel field-effect transistor.

Claim 18

The integrated circuit of claim 11, wherein said impedance element comprises an n-channel field-effect series transistor interposed between said precharging circuit and said input terminal; and logic circuitry connected to drive a gate of said series transistor with a signal which varies inversely with the voltage of said input terminal.

Claim 19

A memory in integrated circuit form organized as a matrix in rows and columns and comprising: at least one precharging and reading device associated with one or more rows, said device comprising a precharging element, a current-voltage converter and a read circuit, the selection of an associated row activating the precharging element and connecting the input of said converter to said row, the output of said converter being connected to the precharging element and to the input of the read circuit; and a test circuit connected to isolate the output of the converter from the precharging element and from the reading circuit, apply a test voltage to the output of the converter and measure a current at this output.

Claim 20

A memory in integrated circuit form organized as a matrix in rows and columns and comprising: at least one precharging and reading device associated with one or more rows, said device comprising a precharging element, a current-voltage converter and a read circuit, the selection of an associated row activating the precharging element and connecting the input of said converter to said row, the output of said converter being connected to the precharging element and to the input of the read circuit; and a test circuit connected to isolate the output of the converter from the precharging element and from the reading circuit, apply a test voltage to the output of the converter and measure a current at this output.

Claim 21

The memory of claim 16, wherein said test circuit comprises a transistor controlled by a test signal to cut off the logic supply of the read circuit.

Claim 22

The memory of claim 16, wherein said test circuit comprises a logic gate receiving a test signal to set the precharging element in the inactive state.

Claim 23

The memory of claim 16, wherein the test circuit further comprises another logic gate controlled by a test signal to cut off the input of the converter from its output, the test circuit then enabling the application, by the isolating of the read circuit from the output of the converter, of a test voltage to this output and the measurement therein of the current coming from the precharging element.

Claim 24

The memory of claim 16, the precharging device being connected to an input/output pin of the memory, wherein the test circuit furthermore comprises at least one transistor connected between the output of the converter and said pin and controlled by the test signal applied to the transistor to cut off the supply of the read circuit, apply the test voltage to said input/output pin and measure the current therein.

Claim 27

The method of claim 21, wherein the measurement of the current in the precharging element as a function of a test voltage applied to the output of the converter is carried out by having the reading circuit being inactive and the input of said converter being isolated from its output.