US5898700A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Test signal generator and method for testing a semiconductor wafer having a plurality of memory chips
Assignee: Samsung Electronics Co Ltd
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Filing: 1996-11-12
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Granted: 1999-04-27
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Expires: 2016-11-12
Abstract
Abstract A test signal generator and method for testing a semiconductor wafer having a plurality of memory chips. A plurality of input buffers buffer test timing signals applied through a plurality of input terminals to the memory chips in test mode. A direct current source supplies a direct current of a given level to each of the terminals. The direct current source comprises a MOS transistor for supplying the direct current including a fuse with a first node connected between the terminal and buffer and a second node for receiving the direct current. The fuse is cut by an electric or laser cutter after wafer testing is complete. This enables a probe card for performing the wafer testing to be fabricated with a reduced number of probe tips, thereby overcoming the limitation of a test driver and allowing the simultaneous testing of semiconductor wafers having a plurality of memory chips having different pad configurations.
Inventors
- 👤 Chul-Soo Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 21:51
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/48; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31712; G01R31/31715; G01R31/3181; G01R31/3185; G01R31/318505; G01R31/318511
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
155 words
A test signal generator for testing a semiconductor wafer having a plurality of memory chips, comprising: a plurality of input buffers for buffering the test timing signals applied through a plurality of input terminals to said memory chips in a test mode; and a direct current source coupled to first and second power supply rails of each memory chips for supplying a direct current of a given level to each of said terminals, wherein the direct current source is directly coupled to each of said input terminals; and wherein said direct source comprises a MOS transistor for supplying said direct current, and wherein a gate of MOS transistor is coupled to the first power supply rail and a source of the MOS transistor is coupled to the second power supply rail, and a fuse with a first node directly connected to said terminal and a second node coupled to a drain of the MOS transistor.
Claim 2
Dependent Claim
155 words
A test signal generator for testing a semiconductor wafer having a plurality of memory chips, comprising: a plurality of input buffers for buffering the test timing signals applied through a plurality of input terminals to said memory chips in a test mode; and a direct current source coupled to first and second power supply rails of each memory chips for supplying a direct current of a given level to each of said terminals, wherein the direct current source is directly coupled to each of said input terminals; and wherein said direct source comprises a MOS transistor for supplying said direct current, and wherein a gate of MOS transistor is coupled to the first power supply rail and a source of the MOS transistor is coupled to the second power supply rail, and a fuse with a first node directly connected to said terminal and a second node coupled to a drain of the MOS transistor.
Claim 3
Dependent Claim
22 words
A test signal generator according to claim 1, wherein said fuse is cut by means of electricity or laser after wafer testing.
Claim 4
Dependent Claim
19 words
A test signal generator according to claim 1, wherein said direct current source is connected with a voltage source.
Claim 5
Dependent Claim
127 words
A test signal generator for testing a semiconductor wafer having a plurality of memory chips, comprising: a plurality of input buffers for buffering test timing signals applied through a plurality of input terminals to said memory chips in a test mode; a fuse with one end connected to a transmission line connecting each of said input terminals and a corresponding one of said buffers; and a PMOS transistor including a gate connected to a ground voltage, a source connected to a voltage source and a drain to the other end of said fuse, whereby a voltage level of said input terminal is maintained at a level of said voltage source through said fuse when said source voltage and said ground voltage are applied to the memory chip.
Claim 6
Dependent Claim
127 words
A test signal generator for testing a semiconductor wafer having a plurality of memory chips, comprising: a plurality of input buffers for buffering test timing signals applied through a plurality of input terminals to said memory chips in a test mode; a fuse with one end connected to a transmission line connecting each of said input terminals and a corresponding one of said buffers; and a PMOS transistor including a gate connected to a ground voltage, a source connected to a voltage source and a drain to the other end of said fuse, whereby a voltage level of said input terminal is maintained at a level of said voltage source through said fuse when said source voltage and said ground voltage are applied to the memory chip.
Claim 7
Dependent Claim
22 words
A test signal generator according to claim 4, wherein said fuse is cut by means of electricity or laser after wafer testing.
Claim 8
Dependent Claim
125 words
A test signal generator for testing a semiconductor wafer having a plurality of memory chips, comprising: a plurality of input buffers for buffering test timing signals applied through a plurality of input terminals to said memory chips in a test mode; a fuse with one end connected to a transmission line connecting each of said input terminals and a corresponding one of said buffers; and an NMOS transistor including a gate connected to a voltage source, a drain connected to a ground voltage and a source connected to the other end of said fuse, whereby a voltage level of said input terminal is maintained at the ground voltage through said fuse when said source voltage and said ground voltage are applied to the memory chip.
Claim 9
Dependent Claim
125 words
A test signal generator for testing a semiconductor wafer having a plurality of memory chips, comprising: a plurality of input buffers for buffering test timing signals applied through a plurality of input terminals to said memory chips in a test mode; a fuse with one end connected to a transmission line connecting each of said input terminals and a corresponding one of said buffers; and an NMOS transistor including a gate connected to a voltage source, a drain connected to a ground voltage and a source connected to the other end of said fuse, whereby a voltage level of said input terminal is maintained at the ground voltage through said fuse when said source voltage and said ground voltage are applied to the memory chip.
Claim 10
Dependent Claim
23 words
A test signal generator according to claim 6, wherein said fuse is cut by means of electricity or laser after the wafer testing.
Claim 11
Independent Claim
134 words
A method for testing a semiconductor wafer having a plurality of memory chips, comprising the steps of: associating an input buffer with each of a plurality of input terminals to said memory chips; connecting a test timing signal source to each said input buffer for wafer testing; and supplying a direct current of a given level, responsive to a supply voltage, as a test signal directly to each of said terminals over a transmission line from said test timing signal source; wherein the test timing signal source is a wafer test signal generator, the step of connecting a test timing signal source further comprising connecting the wafer test signal generator to each said input buffer, and further comprising the step of forming the wafer test signal generator from a fuse and a PMOS transistor.
Claim 12
Independent Claim
134 words
A method for testing a semiconductor wafer having a plurality of memory chips, comprising the steps of: associating an input buffer with each of a plurality of input terminals to said memory chips; connecting a test timing signal source to each said input buffer for wafer testing; and supplying a direct current of a given level, responsive to a supply voltage, as a test signal directly to each of said terminals over a transmission line from said test timing signal source; wherein the test timing signal source is a wafer test signal generator, the step of connecting a test timing signal source further comprising connecting the wafer test signal generator to each said input buffer, and further comprising the step of forming the wafer test signal generator from a fuse and a PMOS transistor.
Claim 13
Dependent Claim
18 words
A method according to claim 8, further comprising connecting said wafer test signal generator to a voltage source.
Claim 14
Dependent Claim
12 words
A method according to claim 9, further comprising the step of cutting
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-04-26 | 2002-10-26 | 2003-04-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-26 | 2006-10-26 | 2007-04-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-04-26 | 2010-10-26 | 2011-04-27 | $7700.00 | Window Closed / Lapsed |