US5898629A
Expired / Lapsed
US
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System for stressing a memory integrated circuit die
Assignee: Round Rock Research LLC
•
Filing: 1997-08-21
•
Granted: 1999-04-27
•
Expires: 2017-08-21
Abstract
Abstract A memory self-stress mode capable of use during wafer burn-in such as for dynamic random access memory (DRAM) integrated circuits. A burn-in power supply voltage and ground voltage delivered to a common node of a plurality of memory cell storage capacitors and to an equilibrate node coupled to bit lines. An all row high test cycles word lines between a binary low logic level and a binary high logic level, thereby stressing the dielectric of the memory cell storage capacitors by imposing stress voltages of differing polarity. A half row high test cycles alternate word lines of a word line sequence thereby stressing undesired short circuit connections between adjacent word lines.
Inventors
- 👤 Ray Beffa
- 👤 Leland R. Nevill
- 👤 Warren M. Farnworth
- 👤 Eugene H. Cloud
- 👤 William K. Waller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 21:56
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/50; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C29/56
Claims Analysis
Total Claims: 68
Claim 1
Independent Claim
106 words
A system for stress testing a memory integrated circuit die, the system comprising: burn-in power supply voltage connection capable of coupling a burn-in power supply voltage to a cell plate common node of a memory cell storage capacitor of each memory die of a plurality of memory die on a semiconductor wafer; and ground voltage connection capable of coupling a ground voltage to at least one bit line of a plurality of bit lines of each memory die of the plurality of memory die on the semiconductor wafer and also capable of coupling the bit line to a storage node of the memory cell storage capacitor.
Claim 2
Independent Claim
106 words
A system for stress testing a memory integrated circuit die, the system comprising: burn-in power supply voltage connection capable of coupling a burn-in power supply voltage to a cell plate common node of a memory cell storage capacitor of each memory die of a plurality of memory die on a semiconductor wafer; and ground voltage connection capable of coupling a ground voltage to at least one bit line of a plurality of bit lines of each memory die of the plurality of memory die on the semiconductor wafer and also capable of coupling the bit line to a storage node of the memory cell storage capacitor.
Claim 3
Dependent Claim
53 words
The system of claim 1, further comprising: ground voltage connection capable of coupling a ground voltage to the common cell plate of the memory cell storage capacitor; and burn-in power supply voltage connection capable of coupling a burn-in power supply voltage to at least one bit line of the plurality of bit lines.
Claim 4
Dependent Claim
34 words
The system of claim 2, wherein a particular word line of a plurality of word lines is turned on to couple the bit line to the storage node of the memory cell storage capacitor.
Claim 5
Dependent Claim
39 words
The system of claim 3, wherein the plurality of word lines are arranged in a word line sequence and wherein the turning on of the particular word line comprises turning on each word line in the word line sequence.
Claim 6
Dependent Claim
26 words
The system of claim 1, further comprising a clock signal connection coupled to each memory die of the plurality of memory die on the semiconductor wafer.
Claim 7
Dependent Claim
15 words
The system of claim 1, further comprising an chamber capable of heating the semiconductor wafer.
Claim 8
Dependent Claim
18 words
The system of claim 1, wherein the memory integrated circuit die comprises a dynamic random access memory (DRAM).
Claim 9
Independent Claim
214 words
A system for stress testing a memory integrated circuit die, the system comprising: burn-in power supply voltage connection capable of coupling a burn-in power supply voltage to a cell plate common node of a memory cell storage capacitor of each memory die of a plurality of memory die on a semiconductor wafer; ground voltage connection capable of coupling a ground voltage to at least one bit line of a plurality of bit lines of each memory die of the plurality of memory die on the semiconductor wafer and also capable of coupling the bit line to a storage node of the memory cell storage capacitor; ground voltage connection capable of coupling a ground voltage to the common cell plate of the memory cell storage capacitor; burn-in power supply voltage connection capable of coupling a burn-in power supply voltage to at least one bit line of the plurality of bit lines; wherein a particular word line of a plurality of word lines is turned on to couple the bit line to the storage node of the memory cell storage capacitor; and wherein the plurality of word lines are arranged in a word line sequence and wherein the turning on of the particular word line comprises turning on alternating word lines in the word line sequence.
Claim 10
Independent Claim
214 words
A system for stress testing a memory integrated circuit die, the system comprising: burn-in power supply voltage connection capable of coupling a burn-in power supply voltage to a cell plate common node of a memory cell storage capacitor of each memory die of a plurality of memory die on a semiconductor wafer; ground voltage connection capable of coupling a ground voltage to at least one bit line of a plurality of bit lines of each memory die of the plurality of memory die on the semiconductor wafer and also capable of coupling the bit line to a storage node of the memory cell storage capacitor; ground voltage connection capable of coupling a ground voltage to the common cell plate of the memory cell storage capacitor; burn-in power supply voltage connection capable of coupling a burn-in power supply voltage to at least one bit line of the plurality of bit lines; wherein a particular word line of a plurality of word lines is turned on to couple the bit line to the storage node of the memory cell storage capacitor; and wherein the plurality of word lines are arranged in a word line sequence and wherein the turning on of the particular word line comprises turning on alternating word lines in the word line sequence.
Claim 11
Dependent Claim
18 words
The system of claim 8, further comprising a clock signal connection connected to the memory integrated circuit die.
Claim 12
Dependent Claim
17 words
The system of claim 8, further comprising a chamber capable of heating the memory integrated circuit die.
Claim 13
Dependent Claim
17 words
The system of claim 8, further comprising a chamber capable of cooling the memory integrated circuit die.
Claim 14
Dependent Claim
18 words
The system of claim 8, wherein the memory integrated circuit die comprises a dynamic random access memory (DRAM).
Claim 15
Independent Claim
190 words
A system for stress testing a memory integrated circuit die, the system comprising: burn-in power supply voltage connection capable of coupling a burn-in power supply voltage to a cell plate common node of a memory cell storage capacitor of each memory die of a plurality of memory die on a semiconductor wafer; ground voltage connection capable of coupling a ground voltage to at least one bit line of a plurality of bit lines of each memory die of the plurality of memory die on the semiconductor wafer and also capable of coupling the bit line to a storage node of the memory cell storage capacitor; ground voltage connection capable of coupling a ground voltage to the common cell plate of the memory cell storage capacitor; burn-in power supply voltage connection capable of coupling a burn-in power supply voltage to at least one bit line of the plurality of bit lines; wherein a particular word line of a plurality of word lines is turned on to couple the bit line to the storage node of the memory cell storage capacitor; and a chamber capable of cooling the memory integrated circuit die.
Claim 16
Independent Claim
190 words
A system for stress testing a memory integrated circuit die, the system comprising: burn-in power supply voltage connection capable of coupling a burn-in power supply voltage to a cell plate common node of a memory cell storage capacitor of each memory die of a plurality of memory die on a semiconductor wafer; ground voltage connection capable of coupling a ground voltage to at least one bit line of a plurality of bit lines of each memory die of the plurality of memory die on the semiconductor wafer and also capable of coupling the bit line to a storage node of the memory cell storage capacitor; ground voltage connection capable of coupling a ground voltage to the common cell plate of the memory cell storage capacitor; burn-in power supply voltage connection capable of coupling a burn-in power supply voltage to at least one bit line of the plurality of bit lines; wherein a particular word line of a plurality of word lines is turned on to couple the bit line to the storage node of the memory cell storage capacitor; and a chamber capable of cooling the memory integrated circuit die.
Claim 17
Independent Claim
84 words
A system for stress testing a memory integrated circuit die including a plurality of memory cells, a plurality of bit line, a sequence of word lines, and a common node, with each memory cell coupled to one of the bit lines, one of the word lines, and the common node, the system comprising: means for providing a burn-in voltage differential across the common node and one of the bit lines; and means for turning on alternate word lines of the sequence of word lines.
Claim 18
Independent Claim
84 words
A system for stress testing a memory integrated circuit die including a plurality of memory cells, a plurality of bit line, a sequence of word lines, and a common node, with each memory cell coupled to one of the bit lines, one of the word lines, and the common node, the system comprising: means for providing a burn-in voltage differential across the common node and one of the bit lines; and means for turning on alternate word lines of the sequence of word lines.
Claim 19
Dependent Claim
20 words
The system of claim 14, further comprising: means for reversing polarity of the burn-in voltage differential one or more times.
Claim 20
Dependent Claim
46 words
The system of claim 14, wherein the means for providing the burn-in voltage differential across the common node and one of the bit lines comprises: a burn-in power supply voltage connection to the common node; and a ground voltage connection to one of the bit lines.
Claim 21
Dependent Claim
40 words
The system of claim 14, wherein the means for providing the differential burn-in voltage comprises a conductor on a passivation layer of the memory integrated circuit die, the conductor connected to the common node or to the one bit line.
Claim 22
Dependent Claim
36 words
The system of claim 14, wherein the means for providing the differential burn-in voltage includes a burn-in power supply node on the integrated circuit memory die, which is not used during normal operation of the die.
Claim 23
Dependent Claim
23 words
The system of claim 14, wherein the means for providing the differential burn-in voltage superimposes a clock signal on the differential burn-in voltage.
Claim 24
Independent Claim
114 words
A system of stressing insulation in a memory integrated circuit die on a wafer, the memory integrated circuit die including a plurality of memory cells, a plurality of bit lines, a sequence of word lines, and a common node, with each memory cell coupled to one of the bit lines, to one of the word lines, and to the common node, the system comprising: means for providing a differential burn-in voltage across a pair of adjacent word lines in the word line sequence to stress insulation between the adjacent word lines; and means for reversing polarity of the differential burn-in voltage one or more times to further stress insulation between the adjacent word lines.
Claim 25
Independent Claim
114 words
A system of stressing insulation in a memory integrated circuit die on a wafer, the memory integrated circuit die including a plurality of memory cells, a plurality of bit lines, a sequence of word lines, and a common node, with each memory cell coupled to one of the bit lines, to one of the word lines, and to the common node, the system comprising: means for providing a differential burn-in voltage across a pair of adjacent word lines in the word line sequence to stress insulation between the adjacent word lines; and means for reversing polarity of the differential burn-in voltage one or more times to further stress insulation between the adjacent word lines.
Claim 26
Dependent Claim
31 words
The system of claim 20, further comprising: means for isolating the integrated circuit memory die from the differential burn-in voltage, after the insulation between the pair of adjacent word lines fails.
Claim 27
Dependent Claim
67 words
The system of claim 20, wherein the means for providing the differential burn-in voltage also provides the burn-in voltage differential across the common node and the storage node of one of the memory cells to stress insulation between the common node and the storage node or across one bit line and one word line to stress insulation between the one bit line and the one word line.
Claim 28
Dependent Claim
45 words
The system of claim 20, further comprising: means for isolating the integrated circuit memory die from the differential burn-in voltage after insulation between the common node and the storage node fails, or after insulation between the one bit line and the one word line fails.
Claim 29
Dependent Claim
14 words
The system of claim 23, wherein the means for isolating includes a fusible link.
Claim 30
Dependent Claim
40 words
The system of claim 20, wherein the means for providing the differential burn-in voltage comprises: a conductor on a passivation layer of the memory integrated circuit die, the conductor coupled to the common node or to the one bit line.
Claim 31
Dependent Claim
36 words
The system of claim 20, wherein the means for providing the differential burn-in voltage includes a burn-in power supply node on the integrated circuit memory die, which is not used during normal operation of the die.
Claim 32
Dependent Claim
23 words
The system of claim 20, wherein the means for providing the differential burn-in voltage superimposes a clock signal on the differential burn-in voltage.
Claim 33
Independent Claim
118 words
A system for stressing insulation in a memory integrated circuit die on a wafer, the memory integrated circuit die including a plurality of memory cells, a plurality of bit lines, a sequence of word lines, and a common node, with each memory cell coupled to one of the bit lines, one of the word lines, and the common node, the system comprising: means for providing a burn-in voltage differential across a pair of adjacent word lines in the word line sequence, across the common node and the storage node of one of the memory cells, or across one bit line and one word line; and means for reversing polarity of the burn-in voltage differential one or more times.
Claim 34
Independent Claim
118 words
A system for stressing insulation in a memory integrated circuit die on a wafer, the memory integrated circuit die including a plurality of memory cells, a plurality of bit lines, a sequence of word lines, and a common node, with each memory cell coupled to one of the bit lines, one of the word lines, and the common node, the system comprising: means for providing a burn-in voltage differential across a pair of adjacent word lines in the word line sequence, across the common node and the storage node of one of the memory cells, or across one bit line and one word line; and means for reversing polarity of the burn-in voltage differential one or more times.
Claim 35
Dependent Claim
30 words
The system of claim 28, wherein the means for providing the burn-in voltage differential comprises: means for providing a burn-in power supply voltage; and means for providing a ground voltage.
Claim 36
Dependent Claim
40 words
The system of claim 28, wherein the means for providing the burn-in voltage differential comprises: a conductor on a passivation layer of the memory integrated circuit die, the conductor connected to the common node or to the one bit line.
Claim 37
Dependent Claim
36 words
The system of claim 28, wherein the means for providing the burn-in voltage differential comprises: a burn-in power supply node on the integrated circuit memory die, which is not used during normal operation of the die.
Claim 38
Dependent Claim
23 words
The system of claim 28, wherein the means for providing the burn-in voltage differential superimposes a clock signal on the burn-in voltage differential.
Claim 39
Independent Claim
82 words
A system for stress testing a memory integrated circuit die comprising: burn-in power supply voltage connection connecting a burn-in power supply voltage to a cell plate common node of a memory cell storage capacitor of the memory integrated circuit die; and ground voltage connection connecting a ground voltage to at least one bit line of a plurality of bit lines of the memory integrated circuit die and also connecting the bit line to a storage node of the memory cell storage capacitor.
Claim 40
Independent Claim
82 words
A system for stress testing a memory integrated circuit die comprising: burn-in power supply voltage connection connecting a burn-in power supply voltage to a cell plate common node of a memory cell storage capacitor of the memory integrated circuit die; and ground voltage connection connecting a ground voltage to at least one bit line of a plurality of bit lines of the memory integrated circuit die and also connecting the bit line to a storage node of the memory cell storage capacitor.
Claim 41
Dependent Claim
49 words
The system of claim 33, further comprising: ground voltage connection connecting a ground voltage to the common cell plate of the memory cell storage capacitor; and burn-in power supply voltage connection connecting a burn-in power supply voltage to at least one bit line of the plurality of bit lines.
Claim 42
Dependent Claim
34 words
The system of claim 34, wherein a particular word line of a plurality of word lines is turned on to couple the bit line to the storage node of the memory cell storage capacitor.
Claim 43
Dependent Claim
39 words
The system of claim 35, wherein the plurality of word lines are arranged in a word line sequence and wherein the turning on of the particular word line comprises turning on each word line in the word line sequence.
Claim 44
Dependent Claim
18 words
The system of claim 33, further comprising a clock signal connection coupled to the memory integrated circuit die.
Claim 45
Dependent Claim
17 words
The system of claim 33, further comprising an chamber capable of heating the memory integrated circuit die.
Claim 46
Dependent Claim
18 words
The system of claim 33, wherein the memory integrated circuit die comprises a dynamic random access memory (DRAM).
Claim 47
Independent Claim
47 words
A system for stress testing a memory integrated circuit die comprising: a first voltage source providing a burn-in voltage differential across the common node and one of the bit lines; and a second voltage source for turning on alternate word lines of the sequence of word lines.
Claim 48
Independent Claim
47 words
A system for stress testing a memory integrated circuit die comprising: a first voltage source providing a burn-in voltage differential across the common node and one of the bit lines; and a second voltage source for turning on alternate word lines of the sequence of word lines.
Claim 49
Dependent Claim
18 words
The system of claim 40, wherein polarity of the burn-in voltage differential is reversed one or more times.
Claim 50
Dependent Claim
47 words
The system of claim 40, wherein the first voltage source providing the burn-in voltage differential across the common node and one of the bit lines comprises: a burn-in power supply voltage connection to the common node; and a ground voltage connection to one of the bit lines.
Claim 51
Dependent Claim
41 words
The system of claim 40, wherein the first voltage source providing the differential burn-in voltage comprises a conductor on a passivation layer of the memory integrated circuit die, the conductor connected to the common node or to the one bit line.
Claim 52
Dependent Claim
37 words
The system of claim 40, wherein the first voltage source providing the differential burn-in voltage includes a burn-in power supply node on the integrated circuit memory die, which is not used during normal operation of the die.
Claim 53
Dependent Claim
25 words
The system of claim 40, wherein the first voltage source for providing the differential burn-in voltage superimposes a clock signal on the differential burn-in voltage.
Claim 54
Independent Claim
63 words
A system of stressing insulation in a memory integrated circuit die comprising: a voltage source providing a differential burn-in voltage across a pair of adjacent word lines in the word line sequence to stress insulation between the adjacent word lines; and wherein polarity of the differential burn-in voltage is reversed one or more times to further stress insulation between the adjacent word lines.
Claim 55
Independent Claim
63 words
A system of stressing insulation in a memory integrated circuit die comprising: a voltage source providing a differential burn-in voltage across a pair of adjacent word lines in the word line sequence to stress insulation between the adjacent word lines; and wherein polarity of the differential burn-in voltage is reversed one or more times to further stress insulation between the adjacent word lines.
Claim 56
Dependent Claim
29 words
The system of claim 46, wherein an integrated circuit memory die is isolated from the differential burn-in voltage, after the insulation between the pair of adjacent word lines fails.
Claim 57
Dependent Claim
67 words
The system of claim 46, wherein the voltage source providing the differential burn-in voltage also provides the burn-in voltage differential across the common node and the storage node of one of the memory cells to stress insulation between the common node and the storage node or across one bit line and one word line to stress insulation between the one bit line and the one word line.
Claim 58
Dependent Claim
45 words
The system of claim 46, further comprising: wherein an integrated circuit memory die is isolated from the differential burn-in voltage after insulation between the common node and the storage node fails, or after insulation between the one bit line and the one word line fails.
Claim 59
Dependent Claim
18 words
The system of claim 49, wherein an memory integrated circuit memory die is isolated using a fusible link.
Claim 60
Dependent Claim
40 words
The system of claim 46, wherein the voltage source providing the differential burn-in voltage comprises: a conductor on a passivation layer of the memory integrated circuit die, the conductor coupled to the common node or to the one bit line.
Claim 61
Dependent Claim
36 words
The system of claim 46, wherein the voltage source providing the differential burn-in voltage includes a burn-in power supply node on the memory integrated circuit die, which is not used during normal operation of the die.
Claim 62
Dependent Claim
23 words
The system of claim 46, wherein the voltage source providing the differential burn-in voltage superimposes a clock signal on the differential burn-in voltage.
Claim 63
Independent Claim
69 words
A system for stressing insulation in a memory integrated circuit die comprising: a voltage source providing a burn-in voltage differential across a pair of adjacent word lines in the word line sequence, across the common node and the storage node of one of the memory cells, or across one bit line and one word line; and wherein polarity of the burn-in voltage differential is reversed one or more times.
Claim 64
Independent Claim
69 words
A system for stressing insulation in a memory integrated circuit die comprising: a voltage source providing a burn-in voltage differential across a pair of adjacent word lines in the word line sequence, across the common node and the storage node of one of the memory cells, or across one bit line and one word line; and wherein polarity of the burn-in voltage differential is reversed one or more times.
Claim 65
Dependent Claim
24 words
The system of claim 54, wherein the voltage source providing the burn-in voltage differential comprises: a burn-in power supply voltage; and a ground voltage.
Claim 66
Dependent Claim
40 words
The system of claim 54, wherein the voltage source providing the differential burn-in voltage comprises: a conductor on a passivation layer of the memory integrated circuit die, the conductor connected to the common node or to the one bit line.
Claim 67
Dependent Claim
36 words
The system of claim 54, wherein the voltage source providing the differential burn-in voltage comprises: a burn-in power supply node on the memory integrated circuit die, which is not used during normal operation of the die.
Claim 68
Dependent Claim
23 words
The system of claim 54, wherein the voltage source providing the differential burn-in voltage superimposes a clock signal on the differential burn-in voltage.
References Cited (Backward Citations)
US5294776A
Cited
US5298433A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-04-26 | 2002-10-26 | 2003-04-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-26 | 2006-10-26 | 2007-04-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-04-26 | 2010-10-26 | 2011-04-27 | $7700.00 | Window Closed / Lapsed |