Patent US5896282A successfully refreshed from Google Patents.
US5896282A
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US
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Inverter circuit and integrated uninterruptible power supply protection system
Assignee: Amsdell Inc
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Filing: 1997-07-11
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Granted: 1999-04-20
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Expires: 2017-07-11
Abstract
Abstract An uninterruptible power supply (UPS) system comprising an inverter for converting a DC voltage into an AC voltage comprising a full-bridge circuit having four silicon controlled rectifier (SCR) switches, two pulse control circuits for generating control voltage signals to turn on alternate pairs of said switches, a time sequencing circuit, and a power switch circuit. The full bridge circuit is directly connected to a positive DC input terminal and is coupled through the power switch circuit to a negative DC input terminal. The time sequencing circuit generates a first pulse signal for controlling the first pulse control circuit and a second pulse signal for controlling the second pulse control circuit so that the first pulse signal and the second pulse signal being in phase opposition. The time sequencing circuit further generates a third pulse signal for controlling the power switch circuit. The UPS inverter does not require an iron core transformer and so is of a size and weight which are compatible for use in small type UPS systems. Without sacrificing device size or safe and reliable operation, such a UPS system can be conveniently integrated physically with any standard power supply.
Inventors
- 👤 Fu Ning Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 05:19
CPC Classifications
H; H02; H02M; H02M7/00; H02M7/42; H02M7/44; H02M7/48; H02M7/53; H02M7/537; H02M7/5387; H02M7/53871; H02J; H02J9/00; H02J9/04; H02J9/06; H02J9/061; H02M3/00; H02M3/22; H02M3/24; H02M3/28; H02M3/325; H02M3/335; H02M3/33561; H02M7/505; H02M7/515; H02M7/521; H02M7/523; H02M1/00; H02M1/0083; H02M1/009
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
267 words
An inverter circuit for converting a DC voltage between a first DC input and a second DC input into an AC voltage having first and second half cycles of opposite polarity across a load, said load being coupled between a first output terminal and a second output terminal, the inverter circuit comprising: (a) a bridge circuit comprising a plurality of silicon controlled rectifier switches arranged in a bridge configuration, said bridge circuit being coupled between said first DC input and a first node, said bridge circuit further being coupled to said first output terminal and said second output terminal; (b) a power switch circuit responsive to a third pulse signal and coupled between said first node and said second DC input, said power switch circuit including circuitry which provides overload and short circuit protection by limiting the magnitude of current through said load; (c) a first pulse control circuit responsive to a first pulse signal and coupled to said bridge circuit for turning on a first portion of said bridge circuit; (d) a second pulse control circuit responsive to a second pulse signal and coupled to said bridge circuit for turning on a second portion of said bridge circuit; and (e) a timing circuit coupled to said first and second pulse control circuits and to said power switch circuit for generating said first pulse signal for controlling said first pulse control circuit, said second pulse signal for controlling said second pulse control circuit, said first pulse signal and said second pulse signal being in phase opposition, and said third pulse signal for controlling said power switch circuit.
Claim 2
Dependent Claim
267 words
An inverter circuit for converting a DC voltage between a first DC input and a second DC input into an AC voltage having first and second half cycles of opposite polarity across a load, said load being coupled between a first output terminal and a second output terminal, the inverter circuit comprising: (a) a bridge circuit comprising a plurality of silicon controlled rectifier switches arranged in a bridge configuration, said bridge circuit being coupled between said first DC input and a first node, said bridge circuit further being coupled to said first output terminal and said second output terminal; (b) a power switch circuit responsive to a third pulse signal and coupled between said first node and said second DC input, said power switch circuit including circuitry which provides overload and short circuit protection by limiting the magnitude of current through said load; (c) a first pulse control circuit responsive to a first pulse signal and coupled to said bridge circuit for turning on a first portion of said bridge circuit; (d) a second pulse control circuit responsive to a second pulse signal and coupled to said bridge circuit for turning on a second portion of said bridge circuit; and (e) a timing circuit coupled to said first and second pulse control circuits and to said power switch circuit for generating said first pulse signal for controlling said first pulse control circuit, said second pulse signal for controlling said second pulse control circuit, said first pulse signal and said second pulse signal being in phase opposition, and said third pulse signal for controlling said power switch circuit.
Claim 3
Dependent Claim
91 words
An inverter according to claim 1 wherein said bridge circuit comprises first, second, third, and fourth silicon controlled rectifier switches, said first silicon controlled rectifier switch being coupled between said first DC input and said first output terminal, said second silicon controlled rectifier switch being coupled between said first DC input and said second output terminal, said third silicon controlled rectifier switch being coupled between said first node and said second output terminal, and said fourth silicon controlled rectifier switch being coupled between said first node and said first output terminal.
Claim 4
Dependent Claim
49 words
An inverter according to claim 2 wherein said first portion of said bridge circuit comprises said first silicon controlled rectifier switch and said third silicon controlled rectifier switch, and said second portion of said bridge comprises said second silicon controlled rectifier switch and said fourth silicon controlled rectifier switch.
Claim 5
Dependent Claim
67 words
An inverter according to claim 3 wherein the anode of said first silicon controlled rectifier switch and the anode of said second silicon controlled rectifier switch are each connected to said first DC input, the anode of said third silicon controlled rectifier switch is connected to said second output terminal, and the anode of said fourth silicon controlled rectifier switch is connected to said first output terminal.
Claim 6
Dependent Claim
61 words
An inverter according to claim 3 or 4 wherein each of said first, second, third, and fourth silicon controlled rectifier switches is connected in parallel with a diode, such that the anode of the diode is connected to the cathode of the silicon controlled rectifier and the cathode of the diode is connected to the anode of the silicon controlled rectifier.
Claim 7
Dependent Claim
22 words
An inverter according to claim 3 wherein said inverter comprises an inductance coupled between said first node and said power switch circuit.
Claim 8
Dependent Claim
32 words
An inverter according to claim 6 wherein said inverter includes a diode having a first terminal coupled to said power switch circuit and a second terminal coupled to said first DC input.
Claim 9
Dependent Claim
46 words
An inverter according to claim 3, wherein said first output terminal is coupled to said first switch and to said fourth switch through a first inductor and said second output terminal is coupled to said second switch and to said third switch through a second inductor.
Claim 10
Dependent Claim
24 words
An inverter according to claim 3, 6, or 8 wherein a capacitor is coupled between said first output terminal and said second output terminal.
Claim 11
Dependent Claim
277 words
An inverter according to claim 1, wherein each of said first pulse control circuit and said second pulse control circuit comprises a transformer having one primary winding with first and second terminals, a first secondary winding with first and second terminals, and a second secondary winding with first and second terminals, such that: the first terminal of said primary winding is connected to a first reference signal, the second terminal of said primary winding is coupled through a switching circuit to a second reference signal, said switching circuit being responsive to a pulse signal for generating a pulse of a first polarity across said primary winding; the first terminal of said first secondary winding is connected through a first diode to a first terminal of a first capacitor and a first terminal of a first resistor and the second terminal of said first secondary winding is connected to a second terminal of said first capacitor and a second terminal of said first resistor, so that an output pulse is generated between the first terminal and the second terminal of said first resistor in response to said pulse across said primary winding; and the first terminal of said second secondary winding is connected through a second diode to a first terminal of a second capacitor and a first terminal of a second resistor and the second terminal of said second secondary winding is connected to a second terminal of said second capacitor and a second terminal of said second resistor, so that an output pulse is generated between the first terminal and the second terminal of said second resistor in response to said pulse across said primary winding.
Claim 12
Dependent Claim
60 words
An inverter according to claim 10, wherein said first diode and said second diode are configured to isolate said first secondary winding from said first capacitor and from said first resistor and to isolate said second secondary winding from said second capacitor and from said second resistor when said pulse across said primary winding is not of said first polarity.
Claim 13
Dependent Claim
53 words
An inverter according to claim 1, wherein said power switch circuit comprises a power transistor, the drain of said power transistor being connected to said bridge circuit, the source of said power transistor being connected to said second DC input, and the gate of said transistor being coupled to said third pulse signal.
Claim 14
Dependent Claim
206 words
An inverter according to claim 1, wherein said power switch circuit comprises: (a) a first power transistor having a source, gate and drain, the drain of said first power transistor being connected to said bridge circuit, and the gate of said first power transistor being coupled through a first resistor to said third pulse signal; (b) a second power transistor having a source, gate and drain, the gate of said second power transistor being coupled to said third pulse signal and the source of said second power transistor being coupled to the source of said first power transistor; (c) a third transistor having a base; (d) a second resistor coupled between the source of said first power transistor and the base of said third transistor; (e) a third resistor coupled between the source of said second power transistor and the second DC input for detecting the magnitude of the current between said first output terminal and said second output terminal; and (f) a fourth resistor coupled between the drain of said first power transistor and the drain of said second power transistor for limiting the magnitude of said current between said first output terminal and said second output terminal when said magnitude exceeds a threshold value.
Claim 15
Dependent Claim
394 words
An inverter circuit for generating an AC voltage having first and second half cycles of opposite polarity and having a wave form of a certain shape, said inverter circuit converting a DC voltage between a first DC input and a second DC input into said AC voltage across a load, said load being coupled between a first output terminal and a second output terminal, said inverter circuit comprising: (a) a bridge circuit comprising a plurality of silicon controlled rectifier switches arranged in a bridge configuration, said bridge circuit being coupled between said first DC input and a first node, said bridge circuit further being coupled to said first output terminal and said second output terminal; (b) a power switch circuit responsive to a third pulse signal and coupled between said first node and said second DC input, said power switch circuit including circuitry which provides overload and short circuit protection by limiting the magnitude of current through said load; (c) a first pulse control circuit responsive to a first pulse signal and coupled to said bridge circuit for turning on a first portion of said bridge circuit; (d) a second pulse control circuit responsive to a second pulse signal and coupled to said bridge circuit for turning on a second portion of said bridge circuit; (e) a timing circuit coupled to said first and second pulse control circuits and to said power switch circuit for generating said first pulse signal for controlling said first pulse control circuit, said second pulse signal for controlling said second pulse control circuit, said first pulse signal and said second pulse signal being in phase opposition, and said third pulse signal for controlling said power switch circuit; (f) a circuit for providing a standard signal in the shape of said wave form; (g) said inverter circuit being configured such that said first pulse signal pulses high and said second pulse signal remains low during the first half cycle of said standard signal; said second pulse signal pulses high and said first pulse signal remains low during the second half cycle of said standard signal; said third pulse signal pulses high if the value of said AC voltage is less than the value of said standard signal; and said third pulse signal remains low if the value of said AC voltage is greater than the value of said standard signal.
Claim 16
Dependent Claim
394 words
An inverter circuit for generating an AC voltage having first and second half cycles of opposite polarity and having a wave form of a certain shape, said inverter circuit converting a DC voltage between a first DC input and a second DC input into said AC voltage across a load, said load being coupled between a first output terminal and a second output terminal, said inverter circuit comprising: (a) a bridge circuit comprising a plurality of silicon controlled rectifier switches arranged in a bridge configuration, said bridge circuit being coupled between said first DC input and a first node, said bridge circuit further being coupled to said first output terminal and said second output terminal; (b) a power switch circuit responsive to a third pulse signal and coupled between said first node and said second DC input, said power switch circuit including circuitry which provides overload and short circuit protection by limiting the magnitude of current through said load; (c) a first pulse control circuit responsive to a first pulse signal and coupled to said bridge circuit for turning on a first portion of said bridge circuit; (d) a second pulse control circuit responsive to a second pulse signal and coupled to said bridge circuit for turning on a second portion of said bridge circuit; (e) a timing circuit coupled to said first and second pulse control circuits and to said power switch circuit for generating said first pulse signal for controlling said first pulse control circuit, said second pulse signal for controlling said second pulse control circuit, said first pulse signal and said second pulse signal being in phase opposition, and said third pulse signal for controlling said power switch circuit; (f) a circuit for providing a standard signal in the shape of said wave form; (g) said inverter circuit being configured such that said first pulse signal pulses high and said second pulse signal remains low during the first half cycle of said standard signal; said second pulse signal pulses high and said first pulse signal remains low during the second half cycle of said standard signal; said third pulse signal pulses high if the value of said AC voltage is less than the value of said standard signal; and said third pulse signal remains low if the value of said AC voltage is greater than the value of said standard signal.
Claim 17
Independent Claim
393 words
A method of using an inverter circuit to generate an AC voltage having first and second half cycles of opposite polarity and having a wave form of a certain shape, said inverter circuit converting a DC voltage between a first DC input and a second DC input into said AC voltage across a load, said load being coupled between a first output terminal and a second output terminal, said inverter circuit comprising: a bridge circuit comprising a plurality of silicon controlled rectifier switches arranged in a bridge configuration, said bridge circuit being coupled between said first DC input and a first node, said bridge circuit further being coupled to said first output terminal and said second output terminal; a power switch circuit responsive to a third pulse signal and coupled between said first node and said second DC input, said power switch circuit including circuitry which provides overload and short circuit protection by limiting the magnitude of current through said load; a first pulse control circuit responsive to a first pulse signal and coupled to said bridge circuit for turning on a first portion of said bridge circuit; a second pulse control circuit responsive to a second pulse signal and coupled to said bridge circuit for turning on a second portion of said bridge circuit; and a timing circuit coupled to said first and second pulse control circuits and to said power switch circuit for generating a first pulse signal for controlling said first pulse control circuit, a second pulse signal for controlling said second pulse control circuit, said first pulse signal and said second pulse signal being in phase opposition, and said third pulse signal for controlling said power switch circuit; said method comprising the steps of: (a) providing a standard signal in the shape of said wave form; (b) pulsing said first pulse signal high and maintaining said second pulse signal low during the first half cycle of said standard signal; (c) pulsing said second pulse signal high and maintaining said first pulse signal low during the second half cycle of said standard signal; (d) pulsing said third pulse signal high if the value of said AC voltage is less than the value of said standard signal; and (e) maintaining said third pulse signal low if the value of said AC voltage is greater than the value of said standard signal.
Claim 18
Independent Claim
393 words
A method of using an inverter circuit to generate an AC voltage having first and second half cycles of opposite polarity and having a wave form of a certain shape, said inverter circuit converting a DC voltage between a first DC input and a second DC input into said AC voltage across a load, said load being coupled between a first output terminal and a second output terminal, said inverter circuit comprising: a bridge circuit comprising a plurality of silicon controlled rectifier switches arranged in a bridge configuration, said bridge circuit being coupled between said first DC input and a first node, said bridge circuit further being coupled to said first output terminal and said second output terminal; a power switch circuit responsive to a third pulse signal and coupled between said first node and said second DC input, said power switch circuit including circuitry which provides overload and short circuit protection by limiting the magnitude of current through said load; a first pulse control circuit responsive to a first pulse signal and coupled to said bridge circuit for turning on a first portion of said bridge circuit; a second pulse control circuit responsive to a second pulse signal and coupled to said bridge circuit for turning on a second portion of said bridge circuit; and a timing circuit coupled to said first and second pulse control circuits and to said power switch circuit for generating a first pulse signal for controlling said first pulse control circuit, a second pulse signal for controlling said second pulse control circuit, said first pulse signal and said second pulse signal being in phase opposition, and said third pulse signal for controlling said power switch circuit; said method comprising the steps of: (a) providing a standard signal in the shape of said wave form; (b) pulsing said first pulse signal high and maintaining said second pulse signal low during the first half cycle of said standard signal; (c) pulsing said second pulse signal high and maintaining said first pulse signal low during the second half cycle of said standard signal; (d) pulsing said third pulse signal high if the value of said AC voltage is less than the value of said standard signal; and (e) maintaining said third pulse signal low if the value of said AC voltage is greater than the value of said standard signal.
Claim 19
Independent Claim
480 words
A method of using an inverter circuit to generate an AC voltage having first and second half cycles of opposite polarity and having a wave form of a certain shape, said inverter circuit converting a voltage between a first input and a second input into said AC voltage across a load, said load being coupled between a first output terminal and a second output terminal, said inverter circuit comprising: a bridge circuit comprising a plurality of silicon controlled rectifier switches arranged in a bridge configuration, said bridge circuit being coupled between said first DC input and a first node, said bridge circuit further being coupled to said first output terminal and said second output terminal; a power switch circuit responsive to a third pulse signal and coupled between said first node and said second DC input, said power switch circuit including circuitry which provides overload and short circuit protection by limiting the magnitude of current through said load; a first pulse control circuit responsive to a first pulse signal and coupled to said bridge circuit for turning on a first portion of said bridge circuit; a second pulse control circuit responsive to a second pulse signal and coupled to said bridge circuit for turning on a second portion of said bridge circuit; and a timing circuit coupled to said first and second pulse control circuits and to said power switch circuit for generating a first pulse signal for controlling said first pulse control circuit, a second pulse signal for controlling said second pulse control circuit, said first pulse signal and said second pulse signal being in phase opposition, and said third pulse signal for controlling said power switch circuit; said method comprising the steps of: (a) providing a standard signal in the shape of said wave form; (b) providing a fully rectified signal at one of said first input or said second input and providing a DC input at the other of said first input or said second input; (c) pulsing said first pulse signal high and maintaining said second pulse signal low during the first half cycle of a standard signal; (d) pulsing said second pulse signal high and maintaining said first pulse signal low during the second half cycle of said standard signal; (e) pulsing said third pulse signal low so as to turn said power switch off during periods between a pulse of said first pulse signal and a pulse of said second pulse signal; (f) increasing the amplitude of said fully rectified signal if the value of said AC voltage is less than the value of said standard signal; and (g) decreasing the amplitude of said fully rectified signal if the value of said AC voltage is greater than the value of said standard signal; such that said fully rectified signal resembles a signal in the shape of said wave form which has been fully rectified.
Claim 20
Independent Claim
480 words
A method of using an inverter circuit to generate an AC voltage having first and second half cycles of opposite polarity and having a wave form of a certain shape, said inverter circuit converting a voltage between a first input and a second input into said AC voltage across a load, said load being coupled between a first output terminal and a second output terminal, said inverter circuit comprising: a bridge circuit comprising a plurality of silicon controlled rectifier switches arranged in a bridge configuration, said bridge circuit being coupled between said first DC input and a first node, said bridge circuit further being coupled to said first output terminal and said second output terminal; a power switch circuit responsive to a third pulse signal and coupled between said first node and said second DC input, said power switch circuit including circuitry which provides overload and short circuit protection by limiting the magnitude of current through said load; a first pulse control circuit responsive to a first pulse signal and coupled to said bridge circuit for turning on a first portion of said bridge circuit; a second pulse control circuit responsive to a second pulse signal and coupled to said bridge circuit for turning on a second portion of said bridge circuit; and a timing circuit coupled to said first and second pulse control circuits and to said power switch circuit for generating a first pulse signal for controlling said first pulse control circuit, a second pulse signal for controlling said second pulse control circuit, said first pulse signal and said second pulse signal being in phase opposition, and said third pulse signal for controlling said power switch circuit; said method comprising the steps of: (a) providing a standard signal in the shape of said wave form; (b) providing a fully rectified signal at one of said first input or said second input and providing a DC input at the other of said first input or said second input; (c) pulsing said first pulse signal high and maintaining said second pulse signal low during the first half cycle of a standard signal; (d) pulsing said second pulse signal high and maintaining said first pulse signal low during the second half cycle of said standard signal; (e) pulsing said third pulse signal low so as to turn said power switch off during periods between a pulse of said first pulse signal and a pulse of said second pulse signal; (f) increasing the amplitude of said fully rectified signal if the value of said AC voltage is less than the value of said standard signal; and (g) decreasing the amplitude of said fully rectified signal if the value of said AC voltage is greater than the value of said standard signal; such that said fully rectified signal resembles a signal in the shape of said wave form which has been fully rectified.
Claim 21
Dependent Claim
82 words
An integrated uninterruptible power supply (UPS) and power supply system for protecting a portable device from disruptions in utility AC power, said portable device having a power supply circuit installed thereon for receiving utility AC power, said integrated UPS and power supply system comprising said power supply circuit and an uninterruptible power supply system circuit, said uninterruptible power supply system circuit comprising a battery and an inverter circuit, said inverter circuit not having an iron core transformer and being of small size.
Claim 22
Dependent Claim
82 words
An integrated uninterruptible power supply (UPS) and power supply system for protecting a portable device from disruptions in utility AC power, said portable device having a power supply circuit installed thereon for receiving utility AC power, said integrated UPS and power supply system comprising said power supply circuit and an uninterruptible power supply system circuit, said uninterruptible power supply system circuit comprising a battery and an inverter circuit, said inverter circuit not having an iron core transformer and being of small size.
Claim 23
Dependent Claim
282 words
An integrated power supply system according to claim 17 wherein said inverter circuit of said uninterruptible power supply system converts a DC voltage between a first DC input and a second DC input into an AC voltage having first and second half cycles of opposite polarity across a load, said load being coupled between a first output terminal and a second output terminal, said inverter circuit comprising: (a) a bridge circuit comprising a plurality of silicon controlled rectifier switches arranged in a bridge configuration, said bridge circuit being coupled between said first DC input and a first node, said bridge circuit further being coupled to said first output terminal and said second output terminal; (b) a power switch circuit responsive to a third pulse signal and coupled between said first node and said second DC input, said power switch circuit including circuitry which provides overload and short circuit protection by limiting the magnitude of current through said load; (c) a first pulse control circuit responsive to a first pulse signal and coupled to said bridge circuit for turning on a first portion of said bridge circuit; (d) a second pulse control circuit responsive to a second pulse signal and coupled to said bridge circuit for turning on a second portion of said bridge circuit; and (e) a timing circuit coupled to said first and second pulse control circuits and to said power switch circuit for generating a first pulse signal for controlling said first pulse control circuit, a second pulse signal for controlling said second pulse control circuit, said first pulse signal and said second pulse signal being in phase opposition, and said third pulse signal for controlling said power switch circuit.
Claim 24
Dependent Claim
94 words
An integrated power supply system according to claim 18 wherein said bridge circuit comprises first, second, third, and fourth silicon controlled rectifier switches, said first silicon controlled rectifier switch being coupled between said first DC input and said first output terminal, said second silicon controlled rectifier switch being coupled between said first DC input and said second output terminal, said third silicon controlled rectifier switch being coupled between said first node and said second output terminal, and said fourth silicon controlled rectifier switch being coupled between said first node and said first output terminal.
Claim 25
Dependent Claim
52 words
An integrated power supply system according to claim 19 wherein said first portion of said bridge circuit comprises said first silicon controlled rectifier switch and said third silicon controlled rectifier switch, and said second portion of said bridge comprises said second silicon controlled rectifier switch and said fourth silicon controlled rectifier switch.
Claim 26
Dependent Claim
24 words
An integrated power supply system according to any of claims 18 to 20 and being installed within said device, said device being a computer.
Claim 27
Dependent Claim
23 words
An inverter circuit according to claim 1 wherein said inverter circuit does not comprise an iron core transformer and is of small size.
Claim 28
Dependent Claim
13 words
An inverter according to claim 9 wherein said load comprises a rectifying circuit.
Claim 29
Dependent Claim
37 words
An inverter according to claim 9 wherein said load has an impedance such that a stable current is maintained through said load when either the first portion or the second portion of said bridge circuit is on.
Claim 30
Dependent Claim
36 words
An inverter according to claim 13 wherein the duration of the leading edge of a half cycle of said AC voltage is determined at least in part by said third resistor and said second power transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-04-19 | 2002-10-19 | 2003-04-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-19 | 2006-10-19 | 2007-04-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-04-19 | 2010-10-19 | 2011-04-20 | $7700.00 | Window Closed / Lapsed |