Data transfer system for transferring data in synchronization with system clock and synchronous semiconductor memory

Claim 2

A data transfer system for transferring data in synchronization with a clock, comprising: a data transfer path that is capable of transferring an a number of data items in parallel simultaneously and that includes pipeline division sections, which can be divided into an N number of pipeline stages, each of the N divided pipeline stages temporarily holding data; and a control section for controlling said pipeline stage division sections, wherein said control section connects (n-1) divisions (n=a/m: m is the number of cycles necessary for data transfer between said divided pipeline stages adjacent to each other) out of n (=N-1) of said pipeline division sections, not separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle corresponding to an a cycle, and activates all of said n pipeline division sections, separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle different from the a cycle.

Claim 3

A data transfer system for transferring data in synchronization with a clock, comprising: a data transfer path capable of transferring an a number of data items in parallel simultaneously; a k number of registers (the k number of registers are assigned numbers ranging from 0 to (k-1), respectively, in the order of data transfer) connected to said data transfer path; a first control section for controlling data transfer from said data transfer path to said registers in such a manner that when the transfer of the a number of data items is started in a cycle corresponding to an a cycle, the first control section causes the a number of data items to be transferred to a group of the register 0 to register (a-1) and a group of register a to register (2a-1) alternately every the a cycle, and when the transfer of the a number of data items is started in a cycle corresponding to an i(mod 2a) cycle away from the a cycle, the first control section recombines said registers and causes the a number of data items to be transferred to a group of register i(mod 2a) to register (i+a-1(mod 2a)) and a group of register (i+a(mod 2a)) to register (i+2a-1(mod 2a)) alternately every the a cycle; and a second control section for controlling data transfer from said registers in such a manner that it transfers data items serially in synchronization with said clock in the order that said registers have been numbered (provided that control returns to register 0 after register (k-1)).

Claim 4

A data transfer system for transferring data in synchronization with a clock, comprising: a data transfer path capable of transferring an a number of data items in parallel simultaneously; a k number of registers (the k number of registers are assigned numbers ranging from 0 to (k-1), respectively, in the order of data transfer) connected to said data transfer path; a first control section for controlling data transfer from said data transfer path to said registers in such a manner that when the transfer of the a number of data items is started in a cycle corresponding to an a cycle, the first control section causes the a number of data items to be transferred to a group of the register 0 to register (a-1) and a group of register a to register (2a-1) alternately every the a cycle, and when the transfer of the a number of data items is started in a cycle corresponding to an i(mod 2a) cycle away from the a cycle, the first control section recombines said registers and causes the a number of data items to be transferred to a group of register i(mod 2a) to register (i+a-1(mod 2a)) and a group of register (i+a(mod 2a)) to register (i+2a-1(mod 2a)) alternately every the a cycle; and a second control section for controlling data transfer from said registers in such a manner that it transfers data items serially in synchronization with said clock in the order that said registers have been numbered (provided that control returns to register 0 after register (k-1)).

Claim 5

A data transfer system for transferring data in synchronization with a clock, comprising: a data transfer path that is capable of transferring an a number of data items in parallel simultaneously and that includes pipeline division sections, which can be divided into an N number of pipeline stages, each of the N divided pipeline stages temporarily holding data; a k number of registers (the k number of registers are assigned numbers ranging from 0 to (k-1), respectively, in the order of data transfer) connected to said data transfer path; a first control section for controlling said pipeline stage division sections, wherein said first control section connects (n-1) divisions (n=a/m: m is the number of cycles necessary for data transfer between said divided pipeline stages adjacent to each other) out of n (=N-1) of said pipeline division sections, not separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle corresponding to an a cycle, and activates all of said n pipeline division sections, separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle corresponding to an i(mod 2a) cycle different from the a cycle; a second control section for controlling data transfer from said data transfer path to said registers in such a manner that when the transfer of the a number of data items is started in the cycle corresponding to the a cycle, the second control section causes the a number of data items to be transferred to a group of register 0 to register (a-1) and a group of register a to register (2a-1) alternately every the a cycle, and when the transfer of the a number of data items is started in the cycle corresponding to the i(mod 2a) cycle different from the a cycle, the second control section recombines said registers and causes the a number of data items to be transferred to a group of register i(mod 2a) to register (i+a-1(mod 2a)) and a group of register (i+a(mod 2a)) to register (i+2a-1(mod 2a)) alternately every the a cycle; and a third control section for controlling data transfer from said registers in such a manner that it transfers data items serially in synchronization with said clock in the order that said registers have been numbered (provided that control returns to register 0 after register (k-1)).

Claim 6

A data transfer system for transferring data in synchronization with a clock, comprising: a data transfer path that is capable of transferring an a number of data items in parallel simultaneously and that includes pipeline division sections, which can be divided into an N number of pipeline stages, each of the N divided pipeline stages temporarily holding data; a k number of registers (the k number of registers are assigned numbers ranging from 0 to (k-1), respectively, in the order of data transfer) connected to said data transfer path; a first control section for controlling said pipeline stage division sections, wherein said first control section connects (n-1) divisions (n=a/m: m is the number of cycles necessary for data transfer between said divided pipeline stages adjacent to each other) out of n (=N-1) of said pipeline division sections, not separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle corresponding to an a cycle, and activates all of said n pipeline division sections, separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle corresponding to an i(mod 2a) cycle different from the a cycle; a second control section for controlling data transfer from said data transfer path to said registers in such a manner that when the transfer of the a number of data items is started in the cycle corresponding to the a cycle, the second control section causes the a number of data items to be transferred to a group of register 0 to register (a-1) and a group of register a to register (2a-1) alternately every the a cycle, and when the transfer of the a number of data items is started in the cycle corresponding to the i(mod 2a) cycle different from the a cycle, the second control section recombines said registers and causes the a number of data items to be transferred to a group of register i(mod 2a) to register (i+a-1(mod 2a)) and a group of register (i+a(mod 2a)) to register (i+2a-1(mod 2a)) alternately every the a cycle; and a third control section for controlling data transfer from said registers in such a manner that it transfers data items serially in synchronization with said clock in the order that said registers have been numbered (provided that control returns to register 0 after register (k-1)).

Claim 7

A data transfer system for transferring data in units of a number of data items in synchronization with a clock, comprising: a data transfer path that transfers the a number of data items in parallel and outputs data a times as fast as the speed of the parallel data transfer in such a manner that it transfers the a number of data items using an a cycle of the clock and outputs the a number of transferred data items at a rate of one data item per cycle of the clock and that includes pipeline division sections, which can be divided into an N number of pipeline stages, each of the N divided pipeline stages temporarily holding data; and a control section for controlling said pipeline stage division sections, wherein said control section connects (n-1) divisions (n=a/m: m is the number of cycles necessary for data transfer between said divided pipeline stages adjacent to each other) out of n (=N-1) of said pipeline division sections, not separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle corresponding to the a cycle, and activates all of said n pipeline division sections, separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle different from the a cycle.

Claim 8

A data transfer system for transferring data in units of a number of data items in synchronization with a clock, comprising: a data transfer path that transfers the a number of data items in parallel and outputs data a times as fast as the speed of the parallel data transfer in such a manner that it transfers the a number of data items using an a cycle of the clock and outputs the a number of transferred data items at a rate of one data item per cycle of the clock and that includes pipeline division sections, which can be divided into an N number of pipeline stages, each of the N divided pipeline stages temporarily holding data; and a control section for controlling said pipeline stage division sections, wherein said control section connects (n-1) divisions (n=a/m: m is the number of cycles necessary for data transfer between said divided pipeline stages adjacent to each other) out of n (=N-1) of said pipeline division sections, not separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle corresponding to the a cycle, and activates all of said n pipeline division sections, separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle different from the a cycle.

Claim 9

A data transfer system for transferring data in units of a number of data items in synchronization with a clock, comprising: a data transfer path that transfers the a number of data items in parallel and outputs data a times as fast as the speed of the parallel data transfer in such a manner that it transfers said a number of data items using an a cycle of the clock and outputs the a number of transferred data items at a rate of one data item per cycle of the clock; a k number of registers (the k number of registers are assigned numbers ranging from 0 to (k-1), respectively, in the order of data transfer) connected to said data transfer path; a first control section for controlling data transfer from said data transfer path to said register in such a manner that when the transfer of the a number of data items is started in a cycle corresponding to the a cycle, the first control section causes the a number of data items to be transferred to a group of register 0 to register (a-1) and a group of register a to register (2a-1) alternately every a cycle, and when the transfer of the a number of data items is started in a cycle corresponding to an i(mod 2a) cycle away from the a cycle, the first control section recombines said registers and causes the a number of data items to be transferred to a group of register i(mod 2a) to register (i+a-1(mod 2a)) and a group of register (i+a(mod 2a)) to register (i+2a-1(mod 2a)) alternately every the a cycle; and a second control section for controlling data transfer from said registers in such a manner that it transfers data items serially in synchronization with the clock in the order that said registers have been numbered (provided that control returns to register 0 after register (k-1)).

Claim 10

A data transfer system for transferring data in units of a number of data items in synchronization with a clock, comprising: a data transfer path that transfers the a number of data items in parallel and outputs data a times as fast as the speed of the parallel data transfer in such a manner that it transfers said a number of data items using an a cycle of the clock and outputs the a number of transferred data items at a rate of one data item per cycle of the clock; a k number of registers (the k number of registers are assigned numbers ranging from 0 to (k-1), respectively, in the order of data transfer) connected to said data transfer path; a first control section for controlling data transfer from said data transfer path to said register in such a manner that when the transfer of the a number of data items is started in a cycle corresponding to the a cycle, the first control section causes the a number of data items to be transferred to a group of register 0 to register (a-1) and a group of register a to register (2a-1) alternately every a cycle, and when the transfer of the a number of data items is started in a cycle corresponding to an i(mod 2a) cycle away from the a cycle, the first control section recombines said registers and causes the a number of data items to be transferred to a group of register i(mod 2a) to register (i+a-1(mod 2a)) and a group of register (i+a(mod 2a)) to register (i+2a-1(mod 2a)) alternately every the a cycle; and a second control section for controlling data transfer from said registers in such a manner that it transfers data items serially in synchronization with the clock in the order that said registers have been numbered (provided that control returns to register 0 after register (k-1)).

Claim 11

A data transfer system for transferring data in units of a number of data items in synchronization with a clock, comprising: a data transfer path that transfers the a number of data items in parallel and outputs data a times as fast as the speed of the parallel data transfer in such a manner that it transfers the a number of data items using an a cycle of the clock and outputs the a number of transferred data items at a rate of one data item per cycle of the clock, and that includes pipeline division sections, which can be divided into an N number of pipeline stages, each of the N divided pipeline stages temporarily holding data; a k number of registers (the k number of registers are assigned numbers ranging from 0 to (k-1), respectively, in the order of data transfer) connected to said data transfer path; a first control section for controlling said pipeline stage division sections, wherein said first control section connects (n-1) divisions (n=a/m: m is the number of cycles necessary for data transfer between said divided pipeline stages adjacent to each other) out of n (=N-1) of said pipeline division sections, not separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle corresponding to the a cycle, and activates all of said n pipeline division sections, separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle corresponding to an i(mod 2a) cycle different from the a cycle; a second control section for controlling data transfer from said data transfer path to said register in such a manner that when the transfer of the a number of data items is started in the cycle corresponding to the a cycle, the second control section causes the a number of data items to be transferred to a group of register 0 to register (a-1) and a group of register a to register (2a-1) alternately every the a cycle, and when the transfer of the a number of data items is started in the cycle i(mod 2a) cycle different from the a cycle, the second control section recombines said registers and causes the a number of data items to be transferred to a group of register i(mod 2a) to register (i+a-1(mod 2a)) and a group of register (i+a(mod 2a)) to register (i+2a-1(mod 2a)) alternately every the a cycle; and a third control section for controlling data transfer from said registers in such a manner that it transfers data items serially in synchronization with the clock in the order that said registers have been numbered (provided that control returns to register 0 after register (k-1)).

Claim 12

A data transfer system for transferring data in units of a number of data items in synchronization with a clock, comprising: a data transfer path that transfers the a number of data items in parallel and outputs data a times as fast as the speed of the parallel data transfer in such a manner that it transfers the a number of data items using an a cycle of the clock and outputs the a number of transferred data items at a rate of one data item per cycle of the clock, and that includes pipeline division sections, which can be divided into an N number of pipeline stages, each of the N divided pipeline stages temporarily holding data; a k number of registers (the k number of registers are assigned numbers ranging from 0 to (k-1), respectively, in the order of data transfer) connected to said data transfer path; a first control section for controlling said pipeline stage division sections, wherein said first control section connects (n-1) divisions (n=a/m: m is the number of cycles necessary for data transfer between said divided pipeline stages adjacent to each other) out of n (=N-1) of said pipeline division sections, not separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle corresponding to the a cycle, and activates all of said n pipeline division sections, separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle corresponding to an i(mod 2a) cycle different from the a cycle; a second control section for controlling data transfer from said data transfer path to said register in such a manner that when the transfer of the a number of data items is started in the cycle corresponding to the a cycle, the second control section causes the a number of data items to be transferred to a group of register 0 to register (a-1) and a group of register a to register (2a-1) alternately every the a cycle, and when the transfer of the a number of data items is started in the cycle i(mod 2a) cycle different from the a cycle, the second control section recombines said registers and causes the a number of data items to be transferred to a group of register i(mod 2a) to register (i+a-1(mod 2a)) and a group of register (i+a(mod 2a)) to register (i+2a-1(mod 2a)) alternately every the a cycle; and a third control section for controlling data transfer from said registers in such a manner that it transfers data items serially in synchronization with the clock in the order that said registers have been numbered (provided that control returns to register 0 after register (k-1)).

Claim 13

A synchronous semiconductor memory device that serially outputs data items at least one by one every cycle of a clock, comprising: address taking-in means for taking an address in the device; decoding means for decoding the taken-in address; a memory cell array composed of a plurality of memory cells for storing data; a data bus electrically connected to said memory cells; transfer means for transferring the one corresponding to said decoded address of the data items stored in said memory cells to said data bus; an output register electrically connected to said data bus; transfer means for transferring the data items transferred to said data bus to said output register in units of a data item at a time; and output means for serially outputting the a data items transferred to said output register in synchronization with said clock, wherein a signal path from said address taking-in means to said output register is divided into N pipeline stages, the data in each pipeline stage is transferred in m cycles of the clock, when data accessing is started in a cycle corresponding to a cycles of said clock, all of said N pipeline stages are not separated from each other and n (=a/m) consecutive ones of said pipeline stages are connected through with each other, and when data accessing is started in a cycle departing from the a cycles of said clock, all of said N pipeline stages are separated from each other.

Claim 14

A synchronous semiconductor memory device that serially outputs data items at least one by one every cycle of a clock, comprising: address taking-in means for taking an address in the device; decoding means for decoding the taken-in address; a memory cell array composed of a plurality of memory cells for storing data; a data bus electrically connected to said memory cells; transfer means for transferring the one corresponding to said decoded address of the data items stored in said memory cells to said data bus; an output register electrically connected to said data bus; transfer means for transferring the data items transferred to said data bus to said output register in units of a data item at a time; and output means for serially outputting the a data items transferred to said output register in synchronization with said clock, wherein a signal path from said address taking-in means to said output register is divided into N pipeline stages, the data in each pipeline stage is transferred in m cycles of the clock, when data accessing is started in a cycle corresponding to a cycles of said clock, all of said N pipeline stages are not separated from each other and n (=a/m) consecutive ones of said pipeline stages are connected through with each other, and when data accessing is started in a cycle departing from the a cycles of said clock, all of said N pipeline stages are separated from each other.

Claim 15

A synchronous semiconductor memory device according to claim 7, wherein said m is one and said n is two and said N is three, said three pipeline stages are composed of a first pipeline stage ranging from the taking in of said address to the decoding, a second pipeline stage ranging until the data corresponding to said decoded address has been transferred to said data bus, and a third pipeline stage ranging until the data items transferred to said data bus has been transferred to said output register in units of a data items at a time, and the pipeline stages connected through when said data accessing is started in a cycle corresponding to the a cycles of said clock are said first pipeline stage and said second pipeline stage.

Claim 16

A synchronous semiconductor memory device that serially outputs data items at least one by one in every cycle of a clock, comprising: address taking-in means for taking an address in the device; decoding means for decoding the taken-in address; a memory cell array composed of a plurality of memory cells for storing data; a data bus electrically connected to said memory cells; transfer means for transferring the one corresponding to said decoded address of the data items stored in said memory cells to said data bus; output registers electrically connected to said data bus; transfer means for transferring the data items transferred to said data bus to said output registers in units of a data items at a time; and output means for serially outputting the a data items transferred to said output registers in synchronization with said clock, wherein the number of said output registers is k and said k output registers are assigned number 0 to number k-1 in accessing order, and said output registers always output the data items cyclically in the order in which said numbers are arranged, when data accessing is started in a cycle corresponding to the a cycles of said clock, the data items transferred to said data bus are alternately transferred in units of a data items to a group of output registers No. 0 to No. a-1 and a group of output registers No. a to No. 2a-1 at regular intervals of a cycles, and when data accessing is started in a cycle departing from i(mod 2a) cycles from the cycle corresponding to the a cycles of said clock, the groups of said output registers are changed and the data items transferred to said data bus are alternately transferred in units of a data items to a group of output registers No. i(mod 2a) to No. i+a-1(mod 2a) and a group of output registers No. i+a(mod 2a) to No. i+2a-1(mod 2a) at regular intervals of a cycles.

Claim 17

A synchronous semiconductor memory device that serially outputs data items at least one by one in every cycle of a clock, comprising: address taking-in means for taking an address in the device; decoding means for decoding the taken-in address; a memory cell array composed of a plurality of memory cells for storing data; a data bus electrically connected to said memory cells; transfer means for transferring the one corresponding to said decoded address of the data items stored in said memory cells to said data bus; output registers electrically connected to said data bus; transfer means for transferring the data items transferred to said data bus to said output registers in units of a data items at a time; and output means for serially outputting the a data items transferred to said output registers in synchronization with said clock, wherein the number of said output registers is k and said k output registers are assigned number 0 to number k-1 in accessing order, and said output registers always output the data items cyclically in the order in which said numbers are arranged, when data accessing is started in a cycle corresponding to the a cycles of said clock, the data items transferred to said data bus are alternately transferred in units of a data items to a group of output registers No. 0 to No. a-1 and a group of output registers No. a to No. 2a-1 at regular intervals of a cycles, and when data accessing is started in a cycle departing from i(mod 2a) cycles from the cycle corresponding to the a cycles of said clock, the groups of said output registers are changed and the data items transferred to said data bus are alternately transferred in units of a data items to a group of output registers No. i(mod 2a) to No. i+a-1(mod 2a) and a group of output registers No. i+a(mod 2a) to No. i+2a-1(mod 2a) at regular intervals of a cycles.

Claim 18

A synchronous semiconductor memory device according to claim 9, wherein said k is four and said a is two.

Claim 19

A synchronous semiconductor memory device that serially outputs data items at least one by one every cycle of a clock, comprising: address taking-in means for taking an address in the device; decoding means for decoding the taken-in address; a memory cell array composed of a plurality of memory cells for storing data; a data bus electrically connected to said memory cells; transfer means for transferring the one corresponding to said decoded address of the data items stored in said memory cells to said data bus; output registers electrically connected to said data bus; transfer means for transferring the data items transferred to said data bus to said output registers in units of a data items at a time; and output means for serially outputting the a data items transferred to said output registers in synchronization with said clock, wherein a signal path from said address taking-in means to said output register is divided into N pipeline stages, the data in each pipeline stage is transferred in m cycles of the clock, when data accessing is started in a cycle corresponding to a cycles of said clock, all of said N pipeline stages are not separated from each other and n (=a/m) consecutive ones of said pipeline stages are connected through with each other, when data accessing is started in a cycle departing from the a cycles of said clock, all of said N pipeline stages are separated from each other, the number of said output registers is k and said k output registers are assigned number 0 to number k-1 in accessing order, and said output registers always output the data cyclically in the order in which said numbers are arranged, when data accessing is started in a cycle corresponding to the a cycles of said clock, the data items transferred to said data bus are alternately transferred in units of a data items to a group of output registers No. 0 to No. a-1 and a group of output registers No. a to No. 2a-1 at regular intervals of a cycles, and when data accessing is started in a cycle departing from i(mod 2a) cycles from the cycle corresponding to the a cycles of said clock, the groups of said output registers are changed and the data items transferred to said data bus are alternately transferred in units of a data items to a group of output registers No. i(mod 2a) to No. i+a-1(mod 2a) and a group of output registers No. i+a(mod 2a) to No. i+2a-1(mod 2a) at regular intervals of a cycles.

Claim 20

A synchronous semiconductor memory device that serially outputs data items at least one by one every cycle of a clock, comprising: address taking-in means for taking an address in the device; decoding means for decoding the taken-in address; a memory cell array composed of a plurality of memory cells for storing data; a data bus electrically connected to said memory cells; transfer means for transferring the one corresponding to said decoded address of the data items stored in said memory cells to said data bus; output registers electrically connected to said data bus; transfer means for transferring the data items transferred to said data bus to said output registers in units of a data items at a time; and output means for serially outputting the a data items transferred to said output registers in synchronization with said clock, wherein a signal path from said address taking-in means to said output register is divided into N pipeline stages, the data in each pipeline stage is transferred in m cycles of the clock, when data accessing is started in a cycle corresponding to a cycles of said clock, all of said N pipeline stages are not separated from each other and n (=a/m) consecutive ones of said pipeline stages are connected through with each other, when data accessing is started in a cycle departing from the a cycles of said clock, all of said N pipeline stages are separated from each other, the number of said output registers is k and said k output registers are assigned number 0 to number k-1 in accessing order, and said output registers always output the data cyclically in the order in which said numbers are arranged, when data accessing is started in a cycle corresponding to the a cycles of said clock, the data items transferred to said data bus are alternately transferred in units of a data items to a group of output registers No. 0 to No. a-1 and a group of output registers No. a to No. 2a-1 at regular intervals of a cycles, and when data accessing is started in a cycle departing from i(mod 2a) cycles from the cycle corresponding to the a cycles of said clock, the groups of said output registers are changed and the data items transferred to said data bus are alternately transferred in units of a data items to a group of output registers No. i(mod 2a) to No. i+a-1(mod 2a) and a group of output registers No. i+a(mod 2a) to No. i+2a-1(mod 2a) at regular intervals of a cycles.

Claim 21

A synchronous semiconductor memory device comprising: an address decoder into which an address is inputted and which decodes the address and outputs a column select signal to a column select line; a latch gate provided in said column select line; bit lines to which a plurality of memory cells are connected and which are selected by said column select signal; a local data bus connected to said bit lines; a select gate that selects said local data bus and connects this bus to a global data bus; output registers that are connected to said global data bus and serially outputs a data items by means of a cycles of a clock; data transfer control means that receives a start signal indicating the start of a new burst in synchronization with said clock and, when receiving the start signal in a cycle other than said a cycles, closes said latch gate; and output register control means that receives a start signal indicating the start of a new burst in synchronization with said clock and, when receiving the start signal in a cycle other than said a cycles, changes the division of the combination of said output registers.

Claim 22

A synchronous semiconductor memory device comprising: an address decoder into which an address is inputted and which decodes the address and outputs a column select signal to a column select line; a latch gate provided in said column select line; bit lines to which a plurality of memory cells are connected and which are selected by said column select signal; a local data bus connected to said bit lines; a select gate that selects said local data bus and connects this bus to a global data bus; output registers that are connected to said global data bus and serially outputs a data items by means of a cycles of a clock; data transfer control means that receives a start signal indicating the start of a new burst in synchronization with said clock and, when receiving the start signal in a cycle other than said a cycles, closes said latch gate; and output register control means that receives a start signal indicating the start of a new burst in synchronization with said clock and, when receiving the start signal in a cycle other than said a cycles, changes the division of the combination of said output registers.

Claim 23

A synchronous semiconductor memory device comprising: a data transfer path which can be divided into at least two pipeline stages and which is connected to a first output register group that serially outputs the data corresponding to the set address by the use of at least two cycles of a burst clock and a second output register group that serially outputs the data by the use of at least other two cycles; sensing means for sensing that an address is reset in the course of a cycle in which either said first output register group or said second output register group outputs the data; pipeline dividing means that divides said data transfer path into at least two pipeline stages in response to a sense instruction from said sensing means and takes said reset address in said divided pipeline stages without waiting for the starting clock of a cycle in which the data in either said first output register group or said second output register group is outputted; division changing means that replaces part of said first output register group with part of said second output register group in response to a sense instruction from said sensing means and thereby produces a new first output register group and a new second output register group; and output means that serially outputs the data corresponding to said reset address from either said new first output register group or said new second output register group by the use of at least two cycles of said burst clock in synchronization with the beginning clock of a cycle in which the data in either said new first output register group or said new second output register group is outputted.

Claim 24

A synchronous semiconductor memory device comprising: a data transfer path which can be divided into at least two pipeline stages and which is connected to a first output register group that serially outputs the data corresponding to the set address by the use of at least two cycles of a burst clock and a second output register group that serially outputs the data by the use of at least other two cycles; sensing means for sensing that an address is reset in the course of a cycle in which either said first output register group or said second output register group outputs the data; pipeline dividing means that divides said data transfer path into at least two pipeline stages in response to a sense instruction from said sensing means and takes said reset address in said divided pipeline stages without waiting for the starting clock of a cycle in which the data in either said first output register group or said second output register group is outputted; division changing means that replaces part of said first output register group with part of said second output register group in response to a sense instruction from said sensing means and thereby produces a new first output register group and a new second output register group; and output means that serially outputs the data corresponding to said reset address from either said new first output register group or said new second output register group by the use of at least two cycles of said burst clock in synchronization with the beginning clock of a cycle in which the data in either said new first output register group or said new second output register group is outputted.

Claim 27

A synchronous memory device comprising: a data transfer path that is capable of transferring an a number of data items in parallel simultaneously and that includes pipeline division sections, which can be divided into an N number of pipeline stages, each of the N divided pipeline stages temporarily holding data said data transfer path provided at between address input and data output; and a control section for controlling said pipeline stage division sections, wherein said control section connects (n-1) divisions (n=a/m: m is the number of cycles necessary for data transfer between said divided pipeline stages adjacent to each other) out of n (=N-1) of said pipeline division sections, not separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle corresponding to an a cycle, and activates all of said n pipeline division sections, separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle different from the a cycle.

Claim 28

A synchronous memory device comprising: a data transfer path that is capable of transferring an a number of data items in parallel simultaneously and that includes pipeline division sections, which can be divided into an N number of pipeline stages, each of the N divided pipeline stages temporarily holding data said data transfer path provided at between address input and data output; and a control section for controlling said pipeline stage division sections, wherein said control section connects (n-1) divisions (n=a/m: m is the number of cycles necessary for data transfer between said divided pipeline stages adjacent to each other) out of n (=N-1) of said pipeline division sections, not separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle corresponding to an a cycle, and activates all of said n pipeline division sections, separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle different from the a cycle.

Claim 29

A synchronous memory device comprising: a data transfer path capable of transferring an a number of data items in parallel simultaneously said data transfer path provided at between address input and data output; a k number of registers (the k number of registers are assigned numbers ranging from 0 to (k-1), respectively, in the order of data transfer) connected to said data transfer path; a first control section for controlling data transfer from said data transfer path to said registers in such a manner that when the transfer of the a number of data items is started in a cycle corresponding to an a cycle, the first control section causes the a number of data items to be transferred to a group of the register 0 to register (a-1) and a group of register a to register (2a-1) alternately every the a cycle, and when the transfer of the a number of data items is started in a cycle corresponding to an i(mod 2a) cycle away from the a cycle, the first control section recombines said registers and causes the a number of data items to be transferred to a group of register i(mod 2a) to register (i+a-1(mod 2a)) and a group of register (i+a(mod 2a)) to register (i+2a-1(mod 2a)) alternately every the a cycle; and a second control section for controlling data transfer from said registers in such a manner that it transfers data items serially in synchronization with said clock in the order that said registers have been numbered (provided that control returns to register 0 after register (k-1)).

Claim 30

A synchronous memory device comprising: a data transfer path capable of transferring an a number of data items in parallel simultaneously said data transfer path provided at between address input and data output; a k number of registers (the k number of registers are assigned numbers ranging from 0 to (k-1), respectively, in the order of data transfer) connected to said data transfer path; a first control section for controlling data transfer from said data transfer path to said registers in such a manner that when the transfer of the a number of data items is started in a cycle corresponding to an a cycle, the first control section causes the a number of data items to be transferred to a group of the register 0 to register (a-1) and a group of register a to register (2a-1) alternately every the a cycle, and when the transfer of the a number of data items is started in a cycle corresponding to an i(mod 2a) cycle away from the a cycle, the first control section recombines said registers and causes the a number of data items to be transferred to a group of register i(mod 2a) to register (i+a-1(mod 2a)) and a group of register (i+a(mod 2a)) to register (i+2a-1(mod 2a)) alternately every the a cycle; and a second control section for controlling data transfer from said registers in such a manner that it transfers data items serially in synchronization with said clock in the order that said registers have been numbered (provided that control returns to register 0 after register (k-1)).

Claim 31

A synchronous memory device comprising: a data transfer path that is capable of transferring an a number of data items in parallel simultaneously and that includes pipeline division sections, which can be divided into an N number of pipeline stages, each of the N divided pipeline stages temporarily holding data said data transfer path provided at between address input and data output; a k number of registers (the k number of registers are assigned numbers ranging from 0 to (k-1), respectively, in the order of data transfer) connected to said data transfer path; a first control section for controlling said pipeline stage division sections, wherein said first control section connects (n-1) divisions (n=a/m: m is the number of cycles necessary for data transfer between said divided pipeline stages adjacent to each other) out of n (=N-1) of said pipeline division sections, not separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle corresponding to an a cycle, and activates all of said n pipeline division sections, separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle corresponding to an i(mod 2a) cycle different from the a cycle; a second control section for controlling data transfer from said data transfer path to said registers in such a manner that when the transfer of the a number of data items is started in the cycle corresponding to the a cycle, the second control section causes the a number of data items to be transferred to a group of register 0 to register (a-1) and a group of register a to register (2a-1) alternately every the a cycle, and when the transfer of the a number of data items is started in the cycle corresponding to the i(mod 2a) cycle different from the a cycle, the second control section recombines said registers and causes the a number of data items to be transferred to a group of register i(mod 2a) to register (i+a-1(mod 2a)) and a group of register (i+a(mod 2a)) to register (i+2a-1(mod 2a)) alternately every the a cycle; and a third control section for controlling data transfer from said registers in such a manner that it transfers data items serially in synchronization with said clock in the order that said registers have been numbered (provided that control returns to register 0 after register (k-1)).

Claim 32

A synchronous memory device comprising: a data transfer path that is capable of transferring an a number of data items in parallel simultaneously and that includes pipeline division sections, which can be divided into an N number of pipeline stages, each of the N divided pipeline stages temporarily holding data said data transfer path provided at between address input and data output; a k number of registers (the k number of registers are assigned numbers ranging from 0 to (k-1), respectively, in the order of data transfer) connected to said data transfer path; a first control section for controlling said pipeline stage division sections, wherein said first control section connects (n-1) divisions (n=a/m: m is the number of cycles necessary for data transfer between said divided pipeline stages adjacent to each other) out of n (=N-1) of said pipeline division sections, not separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle corresponding to an a cycle, and activates all of said n pipeline division sections, separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle corresponding to an i(mod 2a) cycle different from the a cycle; a second control section for controlling data transfer from said data transfer path to said registers in such a manner that when the transfer of the a number of data items is started in the cycle corresponding to the a cycle, the second control section causes the a number of data items to be transferred to a group of register 0 to register (a-1) and a group of register a to register (2a-1) alternately every the a cycle, and when the transfer of the a number of data items is started in the cycle corresponding to the i(mod 2a) cycle different from the a cycle, the second control section recombines said registers and causes the a number of data items to be transferred to a group of register i(mod 2a) to register (i+a-1(mod 2a)) and a group of register (i+a(mod 2a)) to register (i+2a-1(mod 2a)) alternately every the a cycle; and a third control section for controlling data transfer from said registers in such a manner that it transfers data items serially in synchronization with said clock in the order that said registers have been numbered (provided that control returns to register 0 after register (k-1)).

Claim 33

A synchronous memory device comprising: a data transfer path for transferring data said data transfer path provided at between address input and data output; a register that converts parallel data transfer into serial data transfer and is provided in said data transfer path; a dividing section for dividing said data transfer path into a plurality of pipeline stages, when data has been transferred in a cycle other than the cycle in which data transfer to said register is limited; an input section that inputs the data transferred in the cycle other than the cycle in which data transfer to said register is limited, to at least the first stage of said divided pipeline stages; and an output section that outputs data serially from said register in a cycle other than the cycle in which data transfer to said register is limited.

Claim 34

A synchronous memory device comprising: a data transfer path for transferring data said data transfer path provided at between address input and data output; a register that converts parallel data transfer into serial data transfer and is provided in said data transfer path; a dividing section for dividing said data transfer path into a plurality of pipeline stages, when data has been transferred in a cycle other than the cycle in which data transfer to said register is limited; an input section that inputs the data transferred in the cycle other than the cycle in which data transfer to said register is limited, to at least the first stage of said divided pipeline stages; and an output section that outputs data serially from said register in a cycle other than the cycle in which data transfer to said register is limited.

Claim 35

A synchronous memory device comprising: a data transfer path that transfers the a number of data items in parallel and outputs data a times as fast as the speed of the parallel data transfer in such a manner that it transfers the a number of data items using an a cycle of the clock and outputs the a number of transferred data items at a rate of one data item per cycle of the clock and that includes pipeline division sections, which can be divided into an N number of pipeline stages, each of the N divided pipeline stages temporarily holding data said data transfer path provided at between address input and data output; and a control section for controlling said pipeline stage division sections, wherein said control section connects (n-1) divisions (n=a/m: m is the number of cycles necessary for data transfer between said divided pipeline stages adjacent to each other) out of n (=N-1) of said pipeline division sections, not separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle corresponding to the a cycle, and activates all of said n pipeline division sections, separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle different from the a cycle.

Claim 36

A synchronous memory device comprising: a data transfer path that transfers the a number of data items in parallel and outputs data a times as fast as the speed of the parallel data transfer in such a manner that it transfers the a number of data items using an a cycle of the clock and outputs the a number of transferred data items at a rate of one data item per cycle of the clock and that includes pipeline division sections, which can be divided into an N number of pipeline stages, each of the N divided pipeline stages temporarily holding data said data transfer path provided at between address input and data output; and a control section for controlling said pipeline stage division sections, wherein said control section connects (n-1) divisions (n=a/m: m is the number of cycles necessary for data transfer between said divided pipeline stages adjacent to each other) out of n (=N-1) of said pipeline division sections, not separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle corresponding to the a cycle, and activates all of said n pipeline division sections, separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle different from the a cycle.

Claim 37

A synchronous memory device comprising: a data transfer path that transfers the a number of data items in parallel and outputs data a times as fast as the speed of the parallel data transfer in such a manner that it transfers said a number of data items using an a cycle of the clock and outputs the a number of transferred data items at a rate of one data item per cycle of the clock said data transfer path provided at between address input and data output; a k number of registers (the k number of registers are assigned numbers ranging from 0 to (k-1), respectively, in the order of data transfer) connected to said data transfer path; a first control section for controlling data transfer from said data transfer path to said register in such a manner that when the transfer of the a number of data items is started in a cycle corresponding to the a cycle, the first control section causes the a number of data items to be transferred to a group of register 0 to register (a-1) and a group of register a to register (2a-1) alternately every a cycle, and when the transfer of the a number of data items is started in a cycle corresponding to an i(mod 2a) cycle away from the a cycle, the first control section recombines said registers and causes the a number of data items to be transferred to a group of register i(mod 2a) to register (i+a-1(mod 2a)) and a group of register (i+a(mod 2a)) to register (i+2a-1(mod 2a)) alternately every the a cycle; and a second control section for controlling data transfer from said registers in such a manner that it transfers data items serially in synchronization with the clock in the order that said registers have been numbered (provided that control returns to register 0 after register (k-1)).

Claim 38

A synchronous memory device comprising: a data transfer path that transfers the a number of data items in parallel and outputs data a times as fast as the speed of the parallel data transfer in such a manner that it transfers said a number of data items using an a cycle of the clock and outputs the a number of transferred data items at a rate of one data item per cycle of the clock said data transfer path provided at between address input and data output; a k number of registers (the k number of registers are assigned numbers ranging from 0 to (k-1), respectively, in the order of data transfer) connected to said data transfer path; a first control section for controlling data transfer from said data transfer path to said register in such a manner that when the transfer of the a number of data items is started in a cycle corresponding to the a cycle, the first control section causes the a number of data items to be transferred to a group of register 0 to register (a-1) and a group of register a to register (2a-1) alternately every a cycle, and when the transfer of the a number of data items is started in a cycle corresponding to an i(mod 2a) cycle away from the a cycle, the first control section recombines said registers and causes the a number of data items to be transferred to a group of register i(mod 2a) to register (i+a-1(mod 2a)) and a group of register (i+a(mod 2a)) to register (i+2a-1(mod 2a)) alternately every the a cycle; and a second control section for controlling data transfer from said registers in such a manner that it transfers data items serially in synchronization with the clock in the order that said registers have been numbered (provided that control returns to register 0 after register (k-1)).

Claim 39

A synchronous memory device comprising: a data transfer path that transfers the a number of data items in parallel and outputs data a times as fast as the speed of the parallel data transfer in such a manner that it transfers the a number of data items using an a cycle of the clock and outputs the a number of transferred data items at a rate of one data item per cycle of the clock, and that includes pipeline division sections, which can be divided into an N number of pipeline stages, each of the N divided pipeline stages temporarily holding data said data transfer path provided at between address input and data output; a k number of registers (the k number of registers are assigned numbers ranging from 0 to (k-1), respectively, in the order of data transfer) connected to said data transfer path; a first control section for controlling said pipeline stage division sections, wherein said first control section connects (n-1) divisions (n=a/m: m is the number of cycles necessary for data transfer between said divided pipeline stages adjacent to each other) out of n (=N-1) of said pipeline division sections, not separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle corresponding to the a cycle, and activates all of said n pipeline division sections, separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle corresponding to an i(mod 2a) cycle different from the a cycle; a second control section for controlling data transfer from said data transfer path to said register in such a manner that when the transfer of the a number of data items is started in the cycle corresponding to the a cycle, the second control section causes the a number of data items to be transferred to a group of register 0 to register (a-1) and a group of register a to register (2a-1) alternately every the a cycle, and when the transfer of the a number of data items is started in the cycle i(mod 2a) cycle different from the a cycle, the second control section recombines said registers and causes the a number of data items to be transferred to a group of register i(mod 2a) to register (i+a-1(mod 2a)) and a group of register (i+a(mod 2a)) to register (i+2a-1(mod 2a)) alternately every the a cycle; and a third control section for controlling data transfer from said registers in such a manner that it transfers data items serially in synchronization with the clock in the order that said registers have been numbered (provided that control returns to register 0 after register (k-1)).

Claim 40

A synchronous memory device comprising: a data transfer path that transfers the a number of data items in parallel and outputs data a times as fast as the speed of the parallel data transfer in such a manner that it transfers the a number of data items using an a cycle of the clock and outputs the a number of transferred data items at a rate of one data item per cycle of the clock, and that includes pipeline division sections, which can be divided into an N number of pipeline stages, each of the N divided pipeline stages temporarily holding data said data transfer path provided at between address input and data output; a k number of registers (the k number of registers are assigned numbers ranging from 0 to (k-1), respectively, in the order of data transfer) connected to said data transfer path; a first control section for controlling said pipeline stage division sections, wherein said first control section connects (n-1) divisions (n=a/m: m is the number of cycles necessary for data transfer between said divided pipeline stages adjacent to each other) out of n (=N-1) of said pipeline division sections, not separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle corresponding to the a cycle, and activates all of said n pipeline division sections, separating all of said N pipeline stages from each other, when the transfer of the a number of data items is started in a cycle corresponding to an i(mod 2a) cycle different from the a cycle; a second control section for controlling data transfer from said data transfer path to said register in such a manner that when the transfer of the a number of data items is started in the cycle corresponding to the a cycle, the second control section causes the a number of data items to be transferred to a group of register 0 to register (a-1) and a group of register a to register (2a-1) alternately every the a cycle, and when the transfer of the a number of data items is started in the cycle i(mod 2a) cycle different from the a cycle, the second control section recombines said registers and causes the a number of data items to be transferred to a group of register i(mod 2a) to register (i+a-1(mod 2a)) and a group of register (i+a(mod 2a)) to register (i+2a-1(mod 2a)) alternately every the a cycle; and a third control section for controlling data transfer from said registers in such a manner that it transfers data items serially in synchronization with the clock in the order that said registers have been numbered (provided that control returns to register 0 after register (k-1)).