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US5894560A Expired / Lapsed US ⏱️ 0.0 years remaining

Method and apparatus for controlling I/O channels responsive to an availability of a plurality of I/O devices to transfer data

Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1996-08-26
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Granted: 1999-04-13
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Expires: 2016-08-26
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Abstract

Abstract An apparatus and method for improving the input/output performance of a computer system under the control of a multi-tasking, multi-threaded operating system. In particular, the invention provides an apparatus and method to chain contiguous DMA scatter gather sub blocks of a PRD table for channel 0 with contiguous DMA scatter gather sub blocks of a PRD table for channel 1, using a single data manager, while maintaining maximum media bandwidth. DMA block transfers are scheduled based on the availability of data from the I/O device's buffer memory, thus minimizing both media or network idle time as well as minimizing I/O bus idle time. Near maximum aggregate bandwidth of multiple I/O buses and their associated devices is obtained. The apparatus and method thus provides significant performance advantages over prior techniques having two I/O channel systems implemented with a single data manager.

Inventors

  • 👤 Richard D. Carmichael
  • 👤 Joel M. Ward
  • 👤 Michael A. Winchell

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 08:19
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/10; G06F13/12; G06F13/122

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 42 words
A method for transferring blocks of data with a plurality of input/output (I/O) devices in a data processing system, comprising the step of: interleaving DMA block transfers responsive to data transfer availability of at least two of the plurality of I/O devices.
Claim 2
Independent Claim 42 words
A method for transferring blocks of data with a plurality of input/output (I/O) devices in a data processing system, comprising the step of: interleaving DMA block transfers responsive to data transfer availability of at least two of the plurality of I/O devices.
Claim 3
Dependent Claim 17 words
The method of claim 1 wherein the interleaving DMA block transfers step uses a single data manager.
Claim 4
Dependent Claim 25 words
The method of claim 1 wherein the interleaving DMA block transfers step is based on actual data availability from the I/O devices during a read.
Claim 5
Dependent Claim 23 words
The method of claim 1 wherein the interleaving DMA block transfers step is based on buffer availability within the I/O devices during writes.
Claim 6
Dependent Claim 29 words
The method of claim 1 wherein the interleaving DMA block transfers step is used to interface two channels of a first bus with a channel of a second bus.
Claim 7
Dependent Claim 28 words
The method of claim 1 wherein slow I/O devices are controlled responsive to a large number of table entries, each table entry having a small block transfer size.
Claim 8
Dependent Claim 28 words
The method of claim 1 wherein faster I/O devices are controlled responsive to a small number of table entries, each table entry having a large block transfer size.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-04-12 2002-10-12 2003-04-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-04-12 2006-10-12 2007-04-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-04-12 2010-10-12 2011-04-13 $7700.00 Window Closed / Lapsed

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