Semiconductor device having test circuit

Claim 2

A semiconductor circuit device, comprising: a semiconductor substrate having a circuit formed therein; a plurality of pads arranged on said semiconductor substrate and around said circuit; a plurality of test circuits arranged between said circuit and said pads, each test circuit having a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal, each said first input terminal being connected to a corresponding one of said pads and each said first output terminal being connected to said circuit, wherein each of said test circuits transfer signals from said pads to said circuit in a normal operation mode; a scan path for serially connecting said test circuits via the second input terminals and the second output terminals thereof; a control section, connected to one end of said scan path, for sequentially supplying test data to said test circuits via said scan path and for generating a first update signal; and a timing converting circuit, connected to said control section, for generating a plurality of second update signals having different delay times based on the first update signal supplied from said control section and supplying the second update signals to the third terminals of said test circuits, wherein each of said test circuits supplies test data to said circuit via the first output terminal thereof in response to one of the second update signals supplied from said timing converting circuit.

Claim 3

A device according to claim 1, wherein said control section includes: a first input terminal for receiving a test instruction for selectively specifying various tests, test data used in the test mode, and a timing converting signal for converting the input timing of the test data; a control circuit supplied with a test mode signal for setting the test mode, said control circuit generating a fetch signal for specifying a fetch of the test instruction, a shift clock signal for shifting the test data, and the first update signal for changing the timing of supply of the test data according to the test mode signal; a first register connected to said control circuit for storing the fetched test instruction; a decoder connected to said first register for decoding the test instruction supplied from said first register; and a first selection circuit having an input terminal connected to said first input terminal, a first output terminal and a second output terminal connected to said scan path, said first selection circuit selecting said first output terminal when the test instruction decoded by said decoder specifies an inputting of the timing converting signal and selecting said second output terminal when the test instruction decoded by said decoder specifies an inputting of test data.

Claim 4

A device according to claim 2, further comprising a second register connected to said first output terminal of said first selection circuit, said second register storing a plurality of timing converting signals output from said first output terminal of said first selection circuit.

Claim 5

A device according to claim 1, wherein said timing converting circuit includes a plurality of delay circuits having different delay times and said delay circuits generate the plurality of second update signals by delaying the first update signal by respective delay times.

Claim 6

A device according to claim 3, wherein each of said test circuits includes: a first selection circuit having a first input terminal connected to a corresponding one of said pads, a second input terminal and an output terminal connected to said circuit, said first selection circuit supplying data input to said first input terminal to said circuit via said output terminal in the normal operation mode; a latch circuit serially connected to another test circuit via said scan path in the test mode, said latch circuit latching the test data transferred via said scan path; a second selection circuit connected to said timing converting circuit and to said second register, said second selection circuit selecting one of the plurality of second update signals supplied from said timing converting circuit according to the timing converting signal supplied from said second register; and a switching circuit connected between said output terminal of said latch circuit and said second input terminal of said first selection circuit, said switching circuit supplying test data latched in said latch circuit to said first selection circuit in response to the second update signal output from said second selection circuit.

Claim 7

A device according to claim 1, wherein said pads are arranged around the periphery of said circuit.

Claim 8

A semiconductor circuit device, comprising: a semiconductor substrate having a circuit formed therein; a plurality of pads formed on said semiconductor substrate; a plurality of test circuits arranged between said circuit and said pads, each test circuit being connected to a corresponding one of said pads and to said circuit for transferring data from the corresponding pad to said circuit in a normal operation mode, and serially connected via a scan path, each of said test circuits having a latch circuit for latching test data transferred via said scan path in a test mode; a control section for outputting a first control signal in the test mode; a generating circuit, connected to said control section, for generating a plurality of second control signals having different output timings in response to the first control signal supplied from said control section; a storing section for storing a plurality of third control signals for selecting the second control signals, the third control signals being supplied to said test circuits; a selection circuit provided in each of said test circuits and connected to said storing section and to said generating circuit, said selection circuit selecting one of the plurality of second control signals supplied from said generating circuit according to one of the third signals stored in said storing section; and a switching circuit providing in each of said test circuits and connected to said selection circuit and to said latch circuit, said switching circuit supplying test data latched in said latch circuit at an output timing of the second control signal which is selected by said selection circuit.

Claim 9

A semiconductor circuit device, comprising: a semiconductor substrate having a circuit formed therein; a plurality of pads formed on said semiconductor substrate; a plurality of test circuits arranged between said circuit and said pads, each test circuit being connected to a corresponding one of said pads and to said circuit for transferring data from the corresponding pad to said circuit in a normal operation mode, and serially connected via a scan path, each of said test circuits having a latch circuit for latching test data transferred via said scan path in a test mode; a control section for outputting a first control signal in the test mode; a generating circuit, connected to said control section, for generating a plurality of second control signals having different output timings in response to the first control signal supplied from said control section; a storing section for storing a plurality of third control signals for selecting the second control signals, the third control signals being supplied to said test circuits; a selection circuit provided in each of said test circuits and connected to said storing section and to said generating circuit, said selection circuit selecting one of the plurality of second control signals supplied from said generating circuit according to one of the third signals stored in said storing section; and a switching circuit providing in each of said test circuits and connected to said selection circuit and to said latch circuit, said switching circuit supplying test data latched in said latch circuit at an output timing of the second control signal which is selected by said selection circuit.

Claim 10

A device according to claim 7, wherein said generating circuit includes a plurality of delay circuits having different delay times which generate the plurality of second control signals by delaying the first control signal.

Claim 11

A device according to claim 7, wherein said control section includes: a first input terminal for receiving a test instruction for selectively specifying various tests, test data used in the test mode, and the third control signals; a control circuit supplied with a test mode signal for setting the test mode, said control circuit generating a fetch signal for specifying a fetch of the test instruction, a shift clock signal for shifting the test data, and the first control signal according to the test mode signal; a register connected to said control circuit for storing the fetched test instruction; a decoder connected to said register for decoding the test instruction supplied from said register; and a first selection circuit having an input terminal connected to said first input terminal, a first output terminal and a second output terminal connected to said scan path, said first selection circuit selecting said first output terminal when the test instruction decoded by said decoder specifies an inputting of one of the third control signals and selecting said second output terminal when the test instruction decoded by said decoder specifies an inputting of test data.

Claim 12

A device according to claim 7, wherein said pads are arranged around the periphery of said circuit.

Claim 13

A semiconductor device, comprising: a semiconductor substrate having a circuit formed therein; a plurality of pads arranged on said semiconductor substrate; a plurality of test circuits arranged between said circuits and said pads, each test circuit being connected to a corresponding one of said pads and to said circuit for supplying signals from the corresponding pad to said circuit; a scan path for serially connecting said test circuits; a control section formed on said semiconductor substrate, said control section including: a first input terminal for receiving a test instruction for selectively specifying various tests, test data used in the test mode, and a timing converting signal for converting the input timing of the test data, a control circuit supplied with a test mode signal for setting the test mode, said control circuit generating a fetch signal for specifying a fetch of the test instruction, a shift clock signal for shifting the test data, and a first update signal for changing the timing of supply of the timing converting signal according to the test mode signal, a first register connected to said control circuit for storing the fetched test instruction, a decoder connected to said first register for decoding the test instruction supplied from said register, and a first selection circuit having an input terminal connected to said first input terminal, a first output terminal and a second output terminal connected to said scan path, said first selection circuit selecting said first output terminal when the test instruction decoded by said decoder specifies an inputting of the timing converting signal and selecting said second output terminal when the test instruction decoded by said decoder specifies an inputting of test data; a second register connected to said first output terminal of said first selection circuit, said second register storing a plurality of timing converting signals output from said first output terminal of said first selection circuit; and a timing converting circuit connected to said control circuit for generating a plurality of second update signals having different delay times, wherein each of said test circuits includes: a second selection circuit having a first input terminal connected to a corresponding one of said pads, a second input terminal and an output terminal connected to said circuit, said second selection circuit supplying data input to said first input terminal to said circuit from said output terminal in a normal operation mode; a latch circuit serially connected to another test circuit via said scan path in the test mode, said latch circuit latching the test data transferred via said scan path; a third selection circuit connected to said timing converting circuit and to said second register, said third selection circuit selecting one of the plurality of second update signals supplied from said timing converting circuit according to the timing converting signal supplied from said second register; and a switching circuit connected between said output terminal of said latch circuit and said second input terminal of said second selection circuit, said switching circuit supplying test data latched in said latch circuit to said second selection circuit in response to the second update signal output from said third selection circuit.

Claim 14

A semiconductor device, comprising: a semiconductor substrate having a circuit formed therein; a plurality of pads arranged on said semiconductor substrate; a plurality of test circuits arranged between said circuits and said pads, each test circuit being connected to a corresponding one of said pads and to said circuit for supplying signals from the corresponding pad to said circuit; a scan path for serially connecting said test circuits; a control section formed on said semiconductor substrate, said control section including: a first input terminal for receiving a test instruction for selectively specifying various tests, test data used in the test mode, and a timing converting signal for converting the input timing of the test data, a control circuit supplied with a test mode signal for setting the test mode, said control circuit generating a fetch signal for specifying a fetch of the test instruction, a shift clock signal for shifting the test data, and a first update signal for changing the timing of supply of the timing converting signal according to the test mode signal, a first register connected to said control circuit for storing the fetched test instruction, a decoder connected to said first register for decoding the test instruction supplied from said register, and a first selection circuit having an input terminal connected to said first input terminal, a first output terminal and a second output terminal connected to said scan path, said first selection circuit selecting said first output terminal when the test instruction decoded by said decoder specifies an inputting of the timing converting signal and selecting said second output terminal when the test instruction decoded by said decoder specifies an inputting of test data; a second register connected to said first output terminal of said first selection circuit, said second register storing a plurality of timing converting signals output from said first output terminal of said first selection circuit; and a timing converting circuit connected to said control circuit for generating a plurality of second update signals having different delay times, wherein each of said test circuits includes: a second selection circuit having a first input terminal connected to a corresponding one of said pads, a second input terminal and an output terminal connected to said circuit, said second selection circuit supplying data input to said first input terminal to said circuit from said output terminal in a normal operation mode; a latch circuit serially connected to another test circuit via said scan path in the test mode, said latch circuit latching the test data transferred via said scan path; a third selection circuit connected to said timing converting circuit and to said second register, said third selection circuit selecting one of the plurality of second update signals supplied from said timing converting circuit according to the timing converting signal supplied from said second register; and a switching circuit connected between said output terminal of said latch circuit and said second input terminal of said second selection circuit, said switching circuit supplying test data latched in said latch circuit to said second selection circuit in response to the second update signal output from said third selection circuit.

Claim 15

A device according to claim 11, wherein said timing converting circuit includes a plurality of delay circuits having different delay times and said delay circuits generate the plurality of second update signals by delaying the first update signal supplied from said control circuit by respective delay times.

Claim 16

A device according to claim 11, wherein said pads are arranged around the periphery of said circuit.

Claim 17

A semiconductor circuit device, comprising: a semiconductor substrate having a circuit formed therein; a plurality of input and a plurality of output pads arranged on said semiconductor substrate; first and second test circuit groups, said first test circuit group including a plurality of test circuits each of which is connected to a corresponding one of said input pads and to said circuit, for supplying signals from said input pads to said circuit in a normal operation mode and said second test circuit group including a plurality of test circuits each of which is connected to a corresponding one of said output pads and to said circuit, for supplying signals output from said circuit to said output pads in the normal operation mode; a scan path for serially connecting said first and second test circuit groups; a control section connected to one end of said scan path for sequentially supplying test data to said first test circuit group via said scan path and generating a first update signal for transferring the test data to said circuit in a test mode; and a timing converting circuit connected to said control section for generating a plurality of second update signals having different delay times based on the first update signal supplied from said control section and supplying the second update signals to each of said first test circuit group, wherein said first test circuit group supplies the test data to said circuit in response to one of the second update signals supplied from said timing converting circuit, and said second test circuit group supplies data output from said circuit to said control section via said scan path.

Claim 18

A semiconductor circuit device, comprising: a semiconductor substrate having a circuit formed therein; a plurality of input and a plurality of output pads arranged on said semiconductor substrate; first and second test circuit groups, said first test circuit group including a plurality of test circuits each of which is connected to a corresponding one of said input pads and to said circuit, for supplying signals from said input pads to said circuit in a normal operation mode and said second test circuit group including a plurality of test circuits each of which is connected to a corresponding one of said output pads and to said circuit, for supplying signals output from said circuit to said output pads in the normal operation mode; a scan path for serially connecting said first and second test circuit groups; a control section connected to one end of said scan path for sequentially supplying test data to said first test circuit group via said scan path and generating a first update signal for transferring the test data to said circuit in a test mode; and a timing converting circuit connected to said control section for generating a plurality of second update signals having different delay times based on the first update signal supplied from said control section and supplying the second update signals to each of said first test circuit group, wherein said first test circuit group supplies the test data to said circuit in response to one of the second update signals supplied from said timing converting circuit, and said second test circuit group supplies data output from said circuit to said control section via said scan path.

Claim 19

A device according to claim 14, wherein said input and output pads are arranged around the periphery of said circuit.

Claim 20

A device according to claim 15, wherein the test circuits of said first and second test circuit groups are arranged between said input and output pads and said circuit.

Claim 21

A semiconductor circuit device, comprising: a circuit; a plurality of pads; a plurality of test circuits arranged between said circuit and said pads, each test circuit having a first input terminal, a second input terminal, a third input terminal, a first output terminal and a second output terminal, each said first input terminal being connected to a corresponding one of said pads and each said first output terminal being connected to said circuit, wherein each of said test circuit transfers signals from said pads to said circuit in a normal operation mode; a scan path for serially connecting said test circuits via the second input terminals and the second output terminals thereof; a control section connected to one end of said scan path for supplying test data to said test circuits via said scan path and for generating a first transfer signal; and a signal generating circuit responsive to the first transfer signal for generating a plurality of second transfer signals having different delay times relative to the first update signal and supplying the second transfer signals to said third terminals of said test circuits, wherein each of said test circuits comprises a first selecting circuit for selecting one of the second transfer signals and supplies test data to said circuit via the first output terminal thereof at a timing based on the selected second transfer signal.

Claim 22

A semiconductor circuit device, comprising: a circuit; a plurality of pads; a plurality of test circuits arranged between said circuit and said pads, each test circuit having a first input terminal, a second input terminal, a third input terminal, a first output terminal and a second output terminal, each said first input terminal being connected to a corresponding one of said pads and each said first output terminal being connected to said circuit, wherein each of said test circuit transfers signals from said pads to said circuit in a normal operation mode; a scan path for serially connecting said test circuits via the second input terminals and the second output terminals thereof; a control section connected to one end of said scan path for supplying test data to said test circuits via said scan path and for generating a first transfer signal; and a signal generating circuit responsive to the first transfer signal for generating a plurality of second transfer signals having different delay times relative to the first update signal and supplying the second transfer signals to said third terminals of said test circuits, wherein each of said test circuits comprises a first selecting circuit for selecting one of the second transfer signals and supplies test data to said circuit via the first output terminal thereof at a timing based on the selected second transfer signal.

Claim 23

A device according to claim 17, wherein each of said test circuits further comprises: a second selecting circuit having a first input terminal for inputting data, a second input terminal, and an output terminal connected to said circuit, said second selecting circuit supplying the data input to said first input terminal to said circuit via said output terminal in a normal operating mode and supplying test data input to said second input terminal to said circuit via said output terminal in a test mode; a latch circuit for storing the test data supplied from said control section; and a switching circuit connected between an output terminal of said latch circuit and said second input terminal of said second selecting circuit, said switching circuit supplying the test data latched in said latch circuit to said second selecting circuit in response to the selected second transfer signal.

Claim 24

A device according to claim 17, wherein said control section comprises: a first input terminal for receiving a test instruction for selectively specifying various tests, test data used in the test mode, and a timing converting signal for converting the input timing of the test data; a control circuit supplied with a test mode signal for setting the test mode, said control circuit generating a fetch signal for specifying a fetch of the test instruction, a shift clock signal for shifting the test data, and the first transfer signal; a first register connected to said control circuit for storing the fetched test instruction; a decoder connected to said first register for decoding the test instruction supplied from said first register; and a second selecting circuit having an input terminal connected to said first input terminal, a first output terminal and a second output terminal connected to said test circuits, said second selecting circuit selecting said first output terminal when the test instruction decoded by said decoder specifies an inputting of the timing converting signal and selecting said second output terminal when the test instruction decoded by said decoder specifies an inputting of test data.

Claim 25

A device according to claim 19, further comprising a second register connected to said first output terminal of said second selecting circuit, said second register storing a plurality of timing conversion signals output from said first output terminal of said second selecting circuit.

Claim 26

A device according to claim 17, wherein said timing signal generating circuit includes a plurality of delay circuits having different delay times and said delay circuits generate the plurality of second transfer signals by delaying the first transfer signal by respective delay times.

Claim 27

A device according to claim 17, further comprising: a scan path for serially connecting said test circuits.