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US5892701A
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Silicon filtering buffer apparatus and the method of operation thereof
Assignee: Tamarack Microelectronics Inc
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Filing: 1996-08-14
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Granted: 1999-04-06
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Expires: 2016-08-14
Abstract
Abstract A silicon active analog filtering buffer apparatus and its method of operation is disclosed to receive an input signal and generates a synthesized output signal. The apparatus comprises a pulse generator for receiving the input signal and producing a sequence of delayed signal pulses in response to the input signal. A control logic circuit is connected to the pulse generator for generating scheduling on/off operation control signals. An array of switched current sources includes a number of switch means each connected to the control logic for receiving a corresponding one of the generated scheduling on/off operation control signals for shaping pre-determined waveforms. An output stage providing an amplified 15 current output for shaping to form the synthesized output signal. No complex computational procedure is necessary for the creation of the output filtered signal. Power consumption, as well as device physical dimensional characteristics are both reduced. Improvements of filter characteristics are achieved.
Inventors
- 👤 Mark Po Shaw Huang
- 👤 Phil Wen Lung Hsieh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 01:25
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03H17/04; H03H2218/00; H03H2218/12
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
148 words
A filtering buffer apparatus receiving an input signal and generating a synthesized output signal, said apparatus comprising: a pulse generator means for receiving said input signal in analog waveform and producing a sequence of delayed signal pulses in response to said input signal; a control logic means connected to said pulse generator means for generating scheduling on/off operation control signals; an array of switched current sources including a plurality of switch means each connected to said control logic for receiving a corresponding one of said generated scheduling on/off operation control signals for shaping pre-determined waveforms; and an output stage connected to said array of switched current sources for providing an amplified current output for shaping to form said synthesized output signal; said output stage including a current summing node, wherein said synthesized output signal is determined by a summation of said current sources each having a different weight.
Claim 2
Dependent Claim
148 words
A filtering buffer apparatus receiving an input signal and generating a synthesized output signal, said apparatus comprising: a pulse generator means for receiving said input signal in analog waveform and producing a sequence of delayed signal pulses in response to said input signal; a control logic means connected to said pulse generator means for generating scheduling on/off operation control signals; an array of switched current sources including a plurality of switch means each connected to said control logic for receiving a corresponding one of said generated scheduling on/off operation control signals for shaping pre-determined waveforms; and an output stage connected to said array of switched current sources for providing an amplified current output for shaping to form said synthesized output signal; said output stage including a current summing node, wherein said synthesized output signal is determined by a summation of said current sources each having a different weight.
Claim 3
Dependent Claim
39 words
The filtering buffer apparatus of claim 1, wherein said pulse generator means comprises an array of a plurality of delay elements connected in cascade, and each of said plurality of delay elements having a corresponding logic gate connected thereto.
Claim 4
Dependent Claim
41 words
The filtering buffer apparatus of claim 2, wherein the output of each of said plurality of delay elements is connected to the input of said corresponding gate logic as well as to the input of the next cascaded delay element stage.
Claim 5
Dependent Claim
18 words
The filtering buffer apparatus of claim 3, wherein said plurality of delay elements are analog signal delay lines.
Claim 6
Dependent Claim
19 words
The filtering buffer apparatus of claim 1, wherein said control logic means comprises two groups of control logic circuits.
Claim 7
Dependent Claim
37 words
The filtering buffer apparatus of claim 5, wherein one group of said control logic circuits controls positively-shaped waveform portion of said synthesized output signal, and the other group controls negatively-shaped waveform portion of said synthesized output signal.
Claim 8
Dependent Claim
21 words
The filtering buffer apparatus of claim 1, wherein said array of switched current sources comprises two groups of switched current sources.
Claim 9
Dependent Claim
39 words
The filtering buffer apparatus of claim 7, wherein one group of said switched current sources switches into positively-shaped waveform portion of said synthesized output signal, and the other group switches into negatively-shaped waveform portion of said synthesized output signal.
Claim 10
Dependent Claim
31 words
The filtering buffer apparatus of claim 1, wherein every current source has a different weight, and the wave form of said synthesized output signal is not limited to sinusoidal wave form.
Claim 11
Dependent Claim
29 words
The filtering buffer apparatus of claim 1, wherein the control logic means ensures a symmetrical output for square wave by scheduling switching in a first on last off manner.
Claim 12
Independent Claim
164 words
A method for generating filtered output in a filtering buffer apparatus, said apparatus receiving an input signal and generating a synthesized output signal, said apparatus comprises a pulse generator means, a control logic means, an array of switched current sources, and an output stage, said method comprising the steps of: said pulse generator means receiving said input signal and producing a sequence of delayed signal pulses in response to said input signal; said control logic means connected to said pulse generator means generating scheduling on/off operation control signals; said array of switched current sources includes a plurality of switch means each connected to said control logic, said array of switched current sources receiving a corresponding one of said generated scheduling on/off operation control signals for shaping pre-determined waveforms; and said output stage providing an amplified current output for shaping to form said synthesized output signal wherein said synthesized output signal is determined by a summation of said current sources each having a different weight.
Claim 13
Independent Claim
164 words
A method for generating filtered output in a filtering buffer apparatus, said apparatus receiving an input signal and generating a synthesized output signal, said apparatus comprises a pulse generator means, a control logic means, an array of switched current sources, and an output stage, said method comprising the steps of: said pulse generator means receiving said input signal and producing a sequence of delayed signal pulses in response to said input signal; said control logic means connected to said pulse generator means generating scheduling on/off operation control signals; said array of switched current sources includes a plurality of switch means each connected to said control logic, said array of switched current sources receiving a corresponding one of said generated scheduling on/off operation control signals for shaping pre-determined waveforms; and said output stage providing an amplified current output for shaping to form said synthesized output signal wherein said synthesized output signal is determined by a summation of said current sources each having a different weight.
Claim 14
Dependent Claim
37 words
The method of claim 11, wherein said pulse generator means comprises an array of a plurality of delay elements connected in cascade, and each of said plurality of delay elements having a corresponding logic gate connected thereto.
Claim 15
Dependent Claim
38 words
The method claim 12, wherein the output of each of said plurality of delay elements is connected to the input of said corresponding logic gate as well as to the input of the next cascaded delay element stage.
Claim 16
Dependent Claim
15 words
The method claim 13, wherein said plurality of delay elements are analog signal delay lines.
Claim 17
Dependent Claim
17 words
The method of claim 11, wherein said control logic means comprises two groups of control logic circuits.
Claim 18
Dependent Claim
34 words
The method claim 15, wherein one group of said control logic circuits controls positively-shaped waveform portion of said synthesized output signal, and the other group controls negatively-shaped waveform portion of said synthesized output signal.
Claim 19
Dependent Claim
19 words
The method of claim 11, wherein said array of switched current sources comprises two groups of switched current sources.
Claim 20
Dependent Claim
37 words
The method of claim 17, wherein one group of said switched current sources switches into positively-shaped waveform portion of said synthesized output signal, and the other group switches into negatively-shaped waveform portion of said synthesized output signal.
Claim 21
Dependent Claim
22 words
The method of claim 18, wherein the output transistor is biasing by a DC current source and operated in class A mode.
Claim 22
Dependent Claim
50 words
The method of claim 11, wherein every current source has a different weight, and the control logic means ensures a symmetrical output for square wave by scheduling switching in a first on last off manner, and the waveform of said synthesized output signal is not limited to sinusodal wave form.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-04-05 | 2002-10-05 | 2003-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-05 | 2006-10-05 | 2007-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-04-05 | 2010-10-05 | 2011-04-06 | $7700.00 | Window Closed / Lapsed |