Patent US5892277A successfully refreshed from Google Patents.
US5892277A
Expired / Lapsed
US
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Tab tape and semiconductor device using the tab tape
Assignee: Toshiba Corp
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Filing: 1997-06-19
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Granted: 1999-04-06
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Expires: 2017-06-19
Abstract
Abstract In a TAB tape, dummy copper foil patterns are provided on the portions of an adhesive on which neither pads nor leads are provided, thereby flattening the upper surface of solder resist coated on the resultant structure.
Inventors
- 👤 Morihiko Ikemizu
- 👤 Takayuki Okutomo
- 👤 Yutaka Fukuoka
- 👤 Masafumi Takeuchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 15:35
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/071; H10W72/90; H05; H05K; H05K3/00; H05K3/30; H05K3/32; H05K3/34; H05K3/3452; H10W70/00; H10W70/40; H10W70/453; H10W70/60; H10W70/67; H10W70/688; H05K1/00; H05K1/02; H05K1/03; H05K1/0393; H05K2201/00; H05K2201/09; H05K2201/09209; H05K2201/09654; H05K2201/09781; H05K2201/10; H05K2201/10613; H05K2201/10621; H05K2201/10681; H10W70/62; H10W70/65; H10W70/654; H10W70/655; H10W72/20; H10W72/29
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
88 words
A semiconductor device comprising: a resin tape; metallic patterns, including pads and leads, formed on the resin tape; solder resist coated on the metallic patterns and on exposed portions of the resin tape between the metallic patterns; and dummy metallic patterns provided in spaces defined between adjacent ones of the metallic patterns and coated with the solder resist, said dummy metallic patterns reducing level differences between upper surfaces of the solder resist, wherein each of the dummy metallic patterns has a width greater than each of the leads.
Claim 2
Dependent Claim
88 words
A semiconductor device comprising: a resin tape; metallic patterns, including pads and leads, formed on the resin tape; solder resist coated on the metallic patterns and on exposed portions of the resin tape between the metallic patterns; and dummy metallic patterns provided in spaces defined between adjacent ones of the metallic patterns and coated with the solder resist, said dummy metallic patterns reducing level differences between upper surfaces of the solder resist, wherein each of the dummy metallic patterns has a width greater than each of the leads.
Claim 3
Dependent Claim
86 words
The semiconductor device according to claim 1, wherein the sum of the thickness of each metallic pattern and the thickness of the portion of the solder resist which is provided on said each metallic pattern is greater, by an amount of from 3 μm to less than 8 μm, than the sum of the thickness of each dummy metallic pattern between corresponding adjacent ones of the metallic patterns and the thickness of the portion of the solder resist which is provided on said each dummy pattern.
Claim 4
Dependent Claim
28 words
The semiconductor device according to claim 1, wherein each dummy metallic pattern is connected to a corresponding one of the pads and a corresponding one of the leads.
Claim 5
Dependent Claim
14 words
The semiconductor device according to claim 1, wherein the dummy metallic patterns are grounded.
Claim 6
Dependent Claim
30 words
The semiconductor device according to claim 1, wherein an adhesive is coated between the resin tape and the metallic patterns and between the resin tape and the dummy metallic patterns.
Claim 7
Dependent Claim
26 words
The semiconductor device according to claim 1, wherein the dummy metallic patterns provided between the pads are not connected to the pads or to the leads.
Claim 8
Dependent Claim
77 words
A semiconductor device comprising: a resin tape; metallic patterns, including pads and leads, formed on the resin tape; solder resist coated on the metallic patterns and on exposed portions of the resin tape between the metallic patterns; and dummy metallic patterns provided in spaces defined between adjacent ones of the pads and the leads and coated with the solder resist, said dummy metallic patterns connected to corresponding ones of the pads and corresponding ones of the leads.
Claim 9
Dependent Claim
77 words
A semiconductor device comprising: a resin tape; metallic patterns, including pads and leads, formed on the resin tape; solder resist coated on the metallic patterns and on exposed portions of the resin tape between the metallic patterns; and dummy metallic patterns provided in spaces defined between adjacent ones of the pads and the leads and coated with the solder resist, said dummy metallic patterns connected to corresponding ones of the pads and corresponding ones of the leads.
Claim 10
Dependent Claim
23 words
The semiconductor device according to claim 7, wherein each of said dummy metallic patterns has a width greater than each of the leads.
Claim 11
Dependent Claim
36 words
The semiconductor device according to claim 7, further comprising: a stiffener adhered to a lower surface of said resin tape; and an adhesive provided between said resin tape and said stiffener, said adhesive having no bubbles.
Claim 12
Dependent Claim
57 words
A semiconductor device comprising: a resin tape; metallic patterns, including pads and leads, formed on the resin tape; solder resist coated on the metallic patterns and on exposed portions of the resin tape between the metallic patterns; and dummy metallic patterns provided between the pads, and coated with the solder resist, said dummy metallic patterns being grounded.
Claim 13
Dependent Claim
57 words
A semiconductor device comprising: a resin tape; metallic patterns, including pads and leads, formed on the resin tape; solder resist coated on the metallic patterns and on exposed portions of the resin tape between the metallic patterns; and dummy metallic patterns provided between the pads, and coated with the solder resist, said dummy metallic patterns being grounded.
Claim 14
Dependent Claim
36 words
The semiconductor device according to claim 10, further comprising: a stiffener adhered to a lower surface of said resin tape; and an adhesive provided between said resin tape and said stiffener, said adhesive having no bubbles.
References Cited (Backward Citations)
US4916514A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-04-05 | 2002-10-05 | 2003-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-05 | 2006-10-05 | 2007-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-04-05 | 2010-10-05 | 2011-04-06 | $7700.00 | Window Closed / Lapsed |