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Patent US5889970A successfully refreshed from Google Patents.
US5889970A
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US
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Dual purpose apparatus, method and system for accelerated graphics port and peripheral component interconnect
Assignee: Hewlett Packard Development Co LP
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Filing: 1997-05-09
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Granted: 1999-03-30
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Expires: 2017-05-09
Abstract
Abstract A core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between an additional peripheral component interconnect ("PCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional PCI bus. A common bus having provisions for the PCI and AGP interface signals is connected to the core logic chip set and either an AGP or PCI device(s). The core logic chip set also has an AGP/PCI arbiter having additional Request ("REQ") and Grant ("GNT") signal lines so that more than one PCI device may be utilized on the additional PCI bus. Selection of the type of bus bridge (AGP or PCI) in the core logic chip set may be made by a hardware signal input, software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of either an AGP or PCI device connected to the common bus.
Inventors
- 👤 Ronald Timothy Horan
- 👤 Sompong Paul Olarig
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 23:15
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/14; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0875; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G5/393; G09G2360/00; G09G2360/12; G09G2360/121
Claims Analysis
Total Claims: 42
Claim 1
Independent Claim
180 words
A computer system having a core logic chip set configurable for either an accelerated graphics port (AGP) bus or an additional peripheral component interconnect (PCI) bus, said system comprising: a central processing unit connected to a host bus; a random access memory connected to a random access memory bus; a core logic chip set connected to the host bus and the random access memory bus; said core logic chip set configured as a first interface bridge between the host bus and the random access memory bus, a second interface bridge between the host bus and a first peripheral component interconnect bus, and a third interface bridge between the random access memory bus and the first peripheral component interconnect bus; said core logic chip set configurable as a fourth interface bridge between the host bus and either an accelerated graphics port bus or a second peripheral component interconnect bus; and said core logic chip set configurable as a fifth interface bridge between the random access memory bus and either the accelerated graphics port bus or the second peripheral component interconnect bus.
Claim 2
Dependent Claim
180 words
A computer system having a core logic chip set configurable for either an accelerated graphics port (AGP) bus or an additional peripheral component interconnect (PCI) bus, said system comprising: a central processing unit connected to a host bus; a random access memory connected to a random access memory bus; a core logic chip set connected to the host bus and the random access memory bus; said core logic chip set configured as a first interface bridge between the host bus and the random access memory bus, a second interface bridge between the host bus and a first peripheral component interconnect bus, and a third interface bridge between the random access memory bus and the first peripheral component interconnect bus; said core logic chip set configurable as a fourth interface bridge between the host bus and either an accelerated graphics port bus or a second peripheral component interconnect bus; and said core logic chip set configurable as a fifth interface bridge between the random access memory bus and either the accelerated graphics port bus or the second peripheral component interconnect bus.
Claim 3
Dependent Claim
18 words
The computer system of claim 1, wherein the central processing unit is a plurality of central processing units.
Claim 4
Dependent Claim
18 words
The computer system of claim 1, wherein the core logic chip set is at least one integrated circuit.
Claim 5
Dependent Claim
25 words
The computer system of claim 3, wherein the at least one integrated circuit core logic chip set is at least one application specific integrated circuit.
Claim 6
Dependent Claim
26 words
The computer system of claim 3, wherein the at least one integrated circuit core logic chip set is at least one programmable logic array integrated circuit.
Claim 7
Dependent Claim
31 words
The computer system of claim 1, further comprising: a video graphics controller connected to the accelerated graphics port bus; and a local frame buffer memory connected to the video graphics controller.
Claim 8
Dependent Claim
21 words
The computer system of claim 1, further comprising: a peripheral component interconnect device connected to the second peripheral component interconnect bus.
Claim 9
Dependent Claim
20 words
The computer system of claim 7, wherein the peripheral component interconnect device is a plurality of peripheral component interconnect devices.
Claim 10
Dependent Claim
38 words
The computer system of claim 1, wherein the host bus, random access memory bus, first peripheral component interconnect bus, and accelerated graphics port bus or second peripheral component interconnect bus are on a computer system printed circuit board.
Claim 11
Dependent Claim
53 words
The computer system of claim 9, wherein the fourth and fifth interface bridges of said core logic chip set are configured for the accelerated graphics port bus by an electrical signal at a first logic level and sent from a hardwired jumper circuit connected on the printed circuit board of the computer system.
Claim 12
Dependent Claim
54 words
The computer system of claim 9, wherein the fourth and fifth interface bridges of said core logic chip set are configured for the second peripheral component interconnect bus by an electrical signal at a second logic level and sent from a hardwired jumper circuit connected on the printed circuit board of the computer system.
Claim 13
Dependent Claim
47 words
The computer system of claim 9, wherein the accelerated graphics port bus and second peripheral component interconnect bus are configured as one common multi-purpose bus sharing common signals on common conductive paths of said multi-purpose bus, said multi-purpose bus located on the computer system printed circuit board.
Claim 14
Dependent Claim
28 words
The computer system of claim 12, wherein said core logic chip set has request and grant signal lines for each peripheral component interconnect device of the computer system.
Claim 15
Dependent Claim
24 words
The computer system of claim 12, wherein an accelerated graphics port connector is on the printed circuit board and connected to said multi-purpose bus.
Claim 16
Dependent Claim
34 words
The computer system of claim 14, further comprising a daughterboard having an edge connector adapted to plug into said accelerated graphics port connector, said daughterboard having at least one peripheral component interconnect connector thereon.
Claim 17
Dependent Claim
45 words
The computer system of claim 15, further comprising an extension connector on the printed circuit board of the computer system, said extension connector connected to said multi-purpose bus, wherein said daughterboard is adapted to plug into said accelerated graphics port connector and said extension connector.
Claim 18
Dependent Claim
26 words
The computer system of claim 12, wherein at least one peripheral component interconnect connector is on the printed circuit board and connected to said multi-purpose bus.
Claim 19
Dependent Claim
32 words
The computer system of claim 12, wherein an accelerated graphics port connector and at least one peripheral component interconnect connector are on the printed circuit board and connected to said multi-purpose bus.
Claim 20
Dependent Claim
40 words
The computer system of claim 18, further comprising an interlock to prevent insertion of an AGP device into the accelerated graphics port connector and a PCI device into the at least one peripheral component interconnect connector at the same time.
Claim 21
Dependent Claim
81 words
The computer system of claim 19, wherein the interlock is a bar slidably attached near said accelerated graphics port connector and said at least one peripheral component interconnect connector, said bar having grooves perpendicular to a long axis thereof the grooves arranged to align with the accelerated graphics port connector when said bar is in a first position and the grooves arranged to align with the at least one peripheral component interconnect connector when said bar is in a second position.
Claim 22
Dependent Claim
52 words
The computer system of claim 20, further comprising an electrically conductive jumper attached to said bar wherein contact is made by the jumper to contacts when said bar is in the first position and contact is not made by the jumper to the contacts when said bar is in the second position.
Claim 23
Dependent Claim
19 words
The computer system of claim 21, wherein the contacts supply a configuration signal to said core logic chip set.
Claim 24
Dependent Claim
21 words
The computer system of claim 20, wherein said bar is slidably moved between the first position and the second position manually.
Claim 25
Dependent Claim
23 words
The computer system of claim 20, wherein said bar is slidably moved between the first position and the second position by electromechanical means.
Claim 26
Dependent Claim
38 words
The computer system of claim 12, wherein said core logic chip set has a bus arbiter having a request signal line and a grant signal line for each AGP device or PCI device connected to said multi-purpose bus.
Claim 27
Dependent Claim
43 words
The computer system of claim 1, wherein the fourth and fifth interface bridges of said core logic chip set are configured for either the accelerated graphics port bus or second peripheral component interconnect bus by software control of said core logic chip set.
Claim 28
Dependent Claim
64 words
The computer system of claim 26, wherein the fourth and fifth interface bridges of said core logic chip set are configured for either the accelerated graphics port bus when an accelerated graphics port device is detected on the accelerated graphics port bus or the second peripheral component interconnect bus when a peripheral component interconnect device is detected on the second peripheral component interconnect bus.
Claim 29
Dependent Claim
25 words
The computer system of claim 27, wherein configuration of said core logic chip set is done during power on self test of the computer system.
Claim 30
Dependent Claim
22 words
The computer system of claim 27, wherein configuration of said core logic chip set is done during configuration of the computer system.
Claim 31
Independent Claim
233 words
A method, in a computer system, of configuring a core logic chip set for either an accelerated graphics port (AGP) bus or an additional peripheral component interconnect (ACI) bus, said method comprising the steps of providing a central processing unit connected to a host bus; providing a random access memory connected to a random access memory bus; providing a core logic chip set connected to the host bus and the random access memory bus; configuring said core logic chip set as a first interface bridge between the host bus and the random access memory bus, a second interface bridge between the host bus and a first peripheral component interconnect bus, and a third interface bridge between the random access memory bus and the first peripheral component interconnect bus; configuring said core logic chip set as a fourth interface bridge between the host bus and an accelerated graphics port bus and a fifth interface bridge between the random access memory bus and the accelerated graphics port bus if a first configuration signal is applied to said core logic chip set; and configuring said core logic chip set as a fourth interface bridge between the host bus and a second peripheral component interconnect bus and a fifth interface bridge between the random access memory bus and the second peripheral component interconnect bus if a second configuration signal is applied to said core logic chip set.
Claim 32
Independent Claim
233 words
A method, in a computer system, of configuring a core logic chip set for either an accelerated graphics port (AGP) bus or an additional peripheral component interconnect (ACI) bus, said method comprising the steps of providing a central processing unit connected to a host bus; providing a random access memory connected to a random access memory bus; providing a core logic chip set connected to the host bus and the random access memory bus; configuring said core logic chip set as a first interface bridge between the host bus and the random access memory bus, a second interface bridge between the host bus and a first peripheral component interconnect bus, and a third interface bridge between the random access memory bus and the first peripheral component interconnect bus; configuring said core logic chip set as a fourth interface bridge between the host bus and an accelerated graphics port bus and a fifth interface bridge between the random access memory bus and the accelerated graphics port bus if a first configuration signal is applied to said core logic chip set; and configuring said core logic chip set as a fourth interface bridge between the host bus and a second peripheral component interconnect bus and a fifth interface bridge between the random access memory bus and the second peripheral component interconnect bus if a second configuration signal is applied to said core logic chip set.
Claim 33
Dependent Claim
32 words
The method of claim 30, wherein the first configuration signal is applied to said core logic chip set when an accelerated graphics port device is detected on the accelerated graphics port bus.
Claim 34
Dependent Claim
23 words
The method of claim 31, wherein the accelerated graphics port device is detected during a power on self test of the computer system.
Claim 35
Dependent Claim
20 words
The method of claim 31, wherein the accelerated graphics port device is detected during a configuration of the computer system.
Claim 36
Dependent Claim
33 words
The method of claim 30, wherein the second configuration signal is applied to said core logic chip set when a peripheral component interconnect device is detected on the second peripheral component interconnect bus.
Claim 37
Dependent Claim
23 words
The method of claim 34, wherein the peripheral component interconnect device is detected during a power on self test of the computer system.
Claim 38
Dependent Claim
20 words
The method of claim 34, wherein the peripheral component interconnect device is detected during a configuration of the computer system.
Claim 39
Dependent Claim
176 words
A core logic chip set configurable for either an accelerated graphics port (AGP) bus or an additional peripheral component interconnect (PCI) bus, comprising: a core logic chip set adapted for connection to a central processing unit host bus, random access memory bus, a first peripheral component interconnect bus, and an accelerated graphics port bus or a second peripheral component interconnect bus; said core logic chip set configured as a first interface bridge between the host bus and the random access memory bus, a second interface bridge between the host bus and the first peripheral component interconnect bus, and a third interface bridge between the random access memory bus and the first peripheral component interconnect bus; said core logic chip set configurable as a fourth interface bridge between the host bus and either the accelerated graphics port bus or the second peripheral component interconnect bus; and said core logic chip set configurable as a fifth interface bridge between the random access memory bus and either the accelerated graphics port bus or the second peripheral component interconnect bus.
Claim 40
Dependent Claim
176 words
A core logic chip set configurable for either an accelerated graphics port (AGP) bus or an additional peripheral component interconnect (PCI) bus, comprising: a core logic chip set adapted for connection to a central processing unit host bus, random access memory bus, a first peripheral component interconnect bus, and an accelerated graphics port bus or a second peripheral component interconnect bus; said core logic chip set configured as a first interface bridge between the host bus and the random access memory bus, a second interface bridge between the host bus and the first peripheral component interconnect bus, and a third interface bridge between the random access memory bus and the first peripheral component interconnect bus; said core logic chip set configurable as a fourth interface bridge between the host bus and either the accelerated graphics port bus or the second peripheral component interconnect bus; and said core logic chip set configurable as a fifth interface bridge between the random access memory bus and either the accelerated graphics port bus or the second peripheral component interconnect bus.
Claim 41
Dependent Claim
36 words
The core logic chip set according to claim 37, wherein connections for the accelerated graphics port bus and second peripheral component interconnect bus share common signals on common conductive paths from said core logic chip set.
Claim 42
Dependent Claim
51 words
The core logic chip set according to claim 37, wherein connections for signals associated with only the accelerated graphics port bus are shared with connections for signals associated with only the second peripheral component interconnect bus so as to reduce the number of connections required for said core logic chip set.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-29 | 2002-09-28 | 2003-03-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-29 | 2006-09-28 | 2007-03-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-29 | 2010-09-28 | 2011-03-30 | $7700.00 | Window Closed / Lapsed |