Patent US5888898A successfully refreshed from Google Patents.
US5888898A
Expired / Lapsed
US
⏱️ 0.0 years remaining
HSQ baking for reduced dielectric constant
Assignee: Advanced Micro Devices Inc
•
Filing: 1997-10-23
•
Granted: 1999-03-30
•
Expires: 2017-10-23
Abstract
Abstract A patterned metal layer is gap filled with HSQ, an oxide formed thereon by PECVD, e.g., silicon dioxide derived from silane and N 2 O, and planarized. The dielectric constant of the HSQ layer is minimized by baking the deposited HSQ layer in an inert atmosphere, e.g., N 2 , before heat soaking in an N 2 O-containing atmosphere for no more than about 10 seconds and subsequent PECVD.
Inventors
- 👤 Minh V. Ngo
- 👤 Khanh Q. Tran
- 👤 Terri J. Kitson
- 👤 Lu You
- 👤 Simon S. Chan
- 👤 Jean Y. Yang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 23:35
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/6922; H10P14/6925; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/6336; H10P14/65; H10P14/6516; H10P14/6529; H10P14/66; H10P14/668; H10P14/6681; H10P14/6682; H10P14/69215; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/093; H10W20/096; H10W20/097; H10W20/40; H10W20/41; H10W20/42; H10W20/45; H10W20/48; H10P14/6342
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
94 words
A method of manufacturing a multilevel semiconductor device, which method comprises: forming a first dielectric interlayer on a substrate; forming a first patterned metal layer, having gaps therein and comprising a first metal feature, on the first dielectric interlayer; depositing a layer of hydrogen silsesquioxane (HSQ) filling the gaps; baking in an inert atmosphere at a temperature of about 400° C.; heat soaking at a temperature of about 400° C. in an oxidizing atmosphere up to about 10 seconds; and depositing an oxide layer on an upper surface of the heat soaked HSQ layer.
Claim 2
Independent Claim
94 words
A method of manufacturing a multilevel semiconductor device, which method comprises: forming a first dielectric interlayer on a substrate; forming a first patterned metal layer, having gaps therein and comprising a first metal feature, on the first dielectric interlayer; depositing a layer of hydrogen silsesquioxane (HSQ) filling the gaps; baking in an inert atmosphere at a temperature of about 400° C.; heat soaking at a temperature of about 400° C. in an oxidizing atmosphere up to about 10 seconds; and depositing an oxide layer on an upper surface of the heat soaked HSQ layer.
Claim 3
Dependent Claim
27 words
The method according to claim 1, comprising baking for about 50 seconds to about 75 seconds in an atmosphere comprising argon, helium, nitrogen, or a mixture thereof.
Claim 4
Dependent Claim
16 words
The method according to claim 2, comprising heat soaking in an atmosphere containing N 2 O.
Claim 5
Dependent Claim
30 words
The method according to claim 3, wherein the oxide layer comprises silicon dioxide derived from silane and deposited by plasma enhanced chemical vapor deposition in an N 2 O atmosphere.
Claim 6
Dependent Claim
30 words
The method according to claim 4, wherein the upper surface of the HSQ layer, after deposition of the silicon dioxide layer, has a dielectric constant no greater than about 3.34.
Claim 7
Dependent Claim
16 words
The method according to claim 5, wherein the dielectric constant is not greater than about 3.27.
Claim 8
Dependent Claim
18 words
The method according to claim 4, comprising depositing the silicon dioxide at a temperature of about 400° C.
Claim 9
Dependent Claim
14 words
The method according to claim 1, further comprising planarizing after depositing the oxide layer.
Claim 10
Dependent Claim
17 words
The method according to claim 1, comprising heat soaking for about 2 seconds to about 10 seconds.
Claim 11
Dependent Claim
92 words
The method according to claim 1, further comprising: depositing a second dielectric interlayer on the first patterned metal layer; forming a borderless through-hole in the second dielectric layer exposing a portion of the first metal feature, the HSQ layer and the oxide layer; filling the through-hole with a conductive material to form a borderless via; and forming a second patterned layer, having gaps therein and comprising a second metal feature, on the second dielectric interlayer, wherein the second metal feature is electrically connected to the first metal feature through the borderless via.
References Cited (Backward Citations)
US5530293A
Cited
US5607773A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-29 | 2002-09-28 | 2003-03-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-29 | 2006-09-28 | 2007-03-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-29 | 2010-09-28 | 2011-03-30 | $7700.00 | Window Closed / Lapsed |