US5886405A
Expired / Lapsed
US
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Semiconductor device package having inner leads with slots
Assignee: Samsung Electronics Co Ltd
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Filing: 1997-08-06
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Granted: 1999-03-23
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Expires: 2017-08-06
Abstract
Abstract A semiconductor device package includes a semiconductor chip and a plurality of inner leads, each having at least one slot formed along an upper surface of the inner lead. An adhesive layer is used to attach a bottom surface of the semiconductor chip to the upper surface of the inner lead. An encapsulant is allowed to flow in a package body mold, around the inner leads and through the slot. The slots prevent the production of turbulence along a side surface of the inner lead opposite to the flow direction, thereby avoiding problems associated with incomplete encapsulation such as the internal voids.
Inventors
- 👤 Tae Hyeong Kim
- 👤 Tae Sung Park
- 👤 In Sik Cho
- 👤 Hee Kook Choi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 22:21
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/40; H10W70/421; H10W70/424; H10W70/411; H10W70/415; H10W74/00; H10W74/01; H10W74/016; H10W72/00; H10W72/071; H10W72/073; H10W72/07351; H10W72/07352; H10W72/30; H10W72/321; H10W72/50; H10W72/531; H10W72/536; H10W72/5363; H10W72/541; H10W72/5445; H10W72/851; H10W72/874; H10W72/884; H10W90/00; H10W90/701; H10W90/731; H10W90/736; H10W90/751; H10W90/756
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
139 words
A semiconductor device package comprising: a plurality of inner leads, each having at least one slot formed along an upper surface of the inner lead; a semiconductor chip disposed on the inner leads, wherein the slots of the plurality of inner leads are spaced apart from an edge of the semiconductor chip; an adhesive means disposed between the semiconductor chip and the plurality of inner leads for attaching a bottom surface of the semiconductor chip to the upper surface of the inner lead; an electrical connection means for electrically connecting the semiconductor chip to the corresponding one of the inner leads; an encapsulant for encapsulating the semiconductor chip, the inner leads, the adhesive means, and the electrical connection means; and a plurality of outer leads formed integrally with corresponding ones of the inner leads and extending from the encapsulant.
Claim 2
Dependent Claim
139 words
A semiconductor device package comprising: a plurality of inner leads, each having at least one slot formed along an upper surface of the inner lead; a semiconductor chip disposed on the inner leads, wherein the slots of the plurality of inner leads are spaced apart from an edge of the semiconductor chip; an adhesive means disposed between the semiconductor chip and the plurality of inner leads for attaching a bottom surface of the semiconductor chip to the upper surface of the inner lead; an electrical connection means for electrically connecting the semiconductor chip to the corresponding one of the inner leads; an encapsulant for encapsulating the semiconductor chip, the inner leads, the adhesive means, and the electrical connection means; and a plurality of outer leads formed integrally with corresponding ones of the inner leads and extending from the encapsulant.
Claim 3
Dependent Claim
15 words
A semiconductor device package of claim 1, wherein said encapsulant is disposed in the slots.
Claim 4
Dependent Claim
22 words
A semiconductor device package of claim 2, wherein a width of each slot is equal to a width of the inner lead.
Claim 5
Dependent Claim
72 words
A semiconductor device package of claim 2, wherein the slot of a lead of the plurality of leads is oriented so that the encapsulant disposed in the slot is contiguous across the lead in a flow direction substantially parallel to a predetermined encapsulating direction, the encapsulating direction defined relative to the semiconductor chip by a line connecting the semiconductor chip in a mold to a gate in the mold during the encapsulating.
Claim 6
Dependent Claim
18 words
A semiconductor device package of claim 3, said slot being formed halfway between edges of said adhesive means.
Claim 7
Dependent Claim
21 words
A semiconductor device package of claim 5, wherein a thickness of each slot is one-half a thickness of the inner lead.
Claim 8
Dependent Claim
27 words
A semiconductor device package of claim 6, wherein a length of each slot is equal to one-third of a distance between the edges of the adhesive means.
Claim 9
Dependent Claim
24 words
A semiconductor device package of claim 1, wherein lower surfaces of distal portions of the inner leads underlying said semiconductor chip are partially etched.
Claim 10
Dependent Claim
23 words
A semiconductor device package of claim 8, wherein said distal portion has a length equal to about one-half a length of a slot.
Claim 11
Dependent Claim
116 words
A semiconductor device package comprising: a semiconductor chip; a plurality of inner leads, each having at least one slot formed along an upper surface of the inner lead; an adhesive means for attaching a bottom surface of the semiconductor chip to the upper surface of the inner lead, wherein said slot is disposed halfway between edges of said adhesive means; an electrical connection means for electrically connecting the semiconductor chip to the corresponding one of the inner leads; an encapsulant for encapsulating the semiconductor chip, the inner leads, the adhesive means, and the electrical connection means; and a plurality of outer leads formed integrally with corresponding ones of the inner leads and extending from the encapsulant.
Claim 12
Dependent Claim
116 words
A semiconductor device package comprising: a semiconductor chip; a plurality of inner leads, each having at least one slot formed along an upper surface of the inner lead; an adhesive means for attaching a bottom surface of the semiconductor chip to the upper surface of the inner lead, wherein said slot is disposed halfway between edges of said adhesive means; an electrical connection means for electrically connecting the semiconductor chip to the corresponding one of the inner leads; an encapsulant for encapsulating the semiconductor chip, the inner leads, the adhesive means, and the electrical connection means; and a plurality of outer leads formed integrally with corresponding ones of the inner leads and extending from the encapsulant.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-22 | 2002-09-21 | 2003-03-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-22 | 2006-09-21 | 2007-03-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-22 | 2010-09-21 | 2011-03-23 | $7700.00 | Window Closed / Lapsed |