Self-registered cylindrical capacitor of high density DRAMs

Claim 1

A method of fabricating at least one capacitor of a DRAM cell, said method comprising the steps of: (a) forming a field oxide region on a semiconductor silicon substrate; (b) forming MOSFET structures on said semiconductor silicon substrate, wherein said MOSFET comprises of gate oxide, gate electrode and drain/source regions; (c) forming a first dielectric layer overlaying the surface of said semiconductor silicon substrate; (d) etching said first dielectric layer to open bitline contact windows for said drain regions of said MOSFET by conventional lithography and plasma-etching techniques; (e) forming a plurality of bitlines covering said bitline contact windows; (f) sequentially forming a second and a third dielectric layer overlaying the entire surface of said silicon substrate; (g) planarizing said third dielectric layer; (h) partially etching remaining of said first dielectric layer, said second and said third dielectric layers to open node contact windows for said source region of said MOSFET by conventional lithography and plasma-etching techniques; (i) depositing a first polysilicon layer overlaying the entire surface of said semiconductor silicon substrate wherein said first polysilicon layer is formed by in-situ doped LPCVD; (j) forming a fourth dielectric layer overlaying said first polysilicon layer; (k) planarizing a portion of said first polysilicon, third and fourth dielectric layers by chemical mechanical polishing; (l) removing the remaining of said third and fourth dielectric layers by HF to expose said first polysilicon layer; (m) dipping into hot phosphoric acid (H 3 PO 4 ) for surface treatment to create a rugged cylindrical storage node surface of said capacitor; and (n) forming a capacitor dielectric layer and a second polysilicon top plate of said capacitor overlaying said first polysilicon storage node by standard integrated circuit processing procedure.

Claim 2

A method of fabricating at least one capacitor of a DRAM cell, said method comprising the steps of: (a) forming a field oxide region on a semiconductor silicon substrate; (b) forming MOSFET structures on said semiconductor silicon substrate, wherein said MOSFET comprises of gate oxide, gate electrode and drain/source regions; (c) forming a first dielectric layer overlaying the surface of said semiconductor silicon substrate; (d) etching said first dielectric layer to open bitline contact windows for said drain regions of said MOSFET by conventional lithography and plasma-etching techniques; (e) forming a plurality of bitlines covering said bitline contact windows; (f) sequentially forming a second and a third dielectric layer overlaying the entire surface of said silicon substrate; (g) planarizing said third dielectric layer; (h) partially etching remaining of said first dielectric layer, said second and said third dielectric layers to open node contact windows for said source region of said MOSFET by conventional lithography and plasma-etching techniques; (i) depositing a first polysilicon layer overlaying the entire surface of said semiconductor silicon substrate wherein said first polysilicon layer is formed by in-situ doped LPCVD; (j) forming a fourth dielectric layer overlaying said first polysilicon layer; (k) planarizing a portion of said first polysilicon, third and fourth dielectric layers by chemical mechanical polishing; (l) removing the remaining of said third and fourth dielectric layers by HF to expose said first polysilicon layer; (m) dipping into hot phosphoric acid (H 3 PO 4 ) for surface treatment to create a rugged cylindrical storage node surface of said capacitor; and (n) forming a capacitor dielectric layer and a second polysilicon top plate of said capacitor overlaying said first polysilicon storage node by standard integrated circuit processing procedure.

Claim 11

A method of forming a polysilicon capacitor structure on a semiconductor silicon substrate having active areas, said method comprising the steps of: (a) forming a first dielectric layer overlaying the surface of said semiconductor silicon substrate, said first dielectric layer conforming to existing topology; (b) depositing a first polysilicon layer overlaying said first dielectric layer wherein said first polysilicon layer is formed by in-situ doped LPCVD; (c) forming a second dielectric layer overlaying said first polysilicon layer; (d) planarizing a portion of said first polysilicon and said second dielectric layers by chemical mechanical polishing; (e) removing the remaining of said second dielectric layer by HF to expose said first polysilicon layer; (f) dipping into hot phosphoric acid (H 3 PO 4 ) for surface treatment to create a rugged cylindrical storage node surface of said capacitor; and (g) forming a capacitor dielectric layer and a second polysilicon top plate of said capacitor overlaying said first polysilicon storage node by standard integrated circuit processing procedure.

Claim 12

A method of forming a polysilicon capacitor structure on a semiconductor silicon substrate having active areas, said method comprising the steps of: (a) forming a first dielectric layer overlaying the surface of said semiconductor silicon substrate, said first dielectric layer conforming to existing topology; (b) depositing a first polysilicon layer overlaying said first dielectric layer wherein said first polysilicon layer is formed by in-situ doped LPCVD; (c) forming a second dielectric layer overlaying said first polysilicon layer; (d) planarizing a portion of said first polysilicon and said second dielectric layers by chemical mechanical polishing; (e) removing the remaining of said second dielectric layer by HF to expose said first polysilicon layer; (f) dipping into hot phosphoric acid (H 3 PO 4 ) for surface treatment to create a rugged cylindrical storage node surface of said capacitor; and (g) forming a capacitor dielectric layer and a second polysilicon top plate of said capacitor overlaying said first polysilicon storage node by standard integrated circuit processing procedure.