Patent US5881009A successfully refreshed from Google Patents.
US5881009A
Expired / Lapsed
US
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Semiconductor memory device
Assignee: Socionext Inc
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Filing: 1997-12-31
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Granted: 1999-03-09
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Expires: 2017-12-31
Abstract
Abstract In the present invention data from the odd memory cell array is latched to a data-hold circuit at a fast timing, which ignores the delay time of the +1 arithmetic circuit, and outputs that data to the output terminal. Further, when the supplied column address is even, data from the even memory cell array is latched to a data-hold circuit at a fast timing similar to that described above, and when the column address is odd, this data is latched to a data-hold circuit with a delay equivalent to the delay of the +1 arithmetic circuit. In this case, since the output of even output data to an output terminal occurs following the output of odd output data, the overall output operation is not affected comparing to the conventional one. Another aspect of the present invention provides a circuit, which shifts one bit combinations of the second and third bits following the least significant bit in a column address. And when the column address is even, the second and third bits address as-is are supplied into an even decoder, and when the column address is odd, supplies a shifted combination of the second and third bits address are supplied to the even decoder. Since this shift operation does not require the same delay time as conventional arithmetic operations, both even and odd CAS delay times can be reduced.
Inventors
- 👤 Hiroyoshi Tomita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:29
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C7/00; G11C7/10; G11C7/1015; G11C7/1018; G11C7/1042
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
163 words
A semiconductor memory device having a 2-bit pre-fetch function, which sequentially outputs first data of a memory cell that corresponds to an externally-supplied or internally-generated first column address, and a second data of a memory cell that corresponds to a second column address, which increments said first column address, comprising: an odd memory cell array, comprising memory cells that correspond to odd column addresses; an odd column address decoder that corresponds to said odd memory cell array; an odd data-hold circuit for holding read data from said odd memory cell array; an even memory cell array, comprising memory cells that correspond to even column addresses; an even column address decoder that corresponds to said even memory cell array; and an even data-hold circuit for holding read data from said even memory cell array; wherein when the least significant bit in said first column address is odd, hold timing of said odd data-hold circuit is faster than hold timing of said even data-hold circuit.
Claim 2
Dependent Claim
163 words
A semiconductor memory device having a 2-bit pre-fetch function, which sequentially outputs first data of a memory cell that corresponds to an externally-supplied or internally-generated first column address, and a second data of a memory cell that corresponds to a second column address, which increments said first column address, comprising: an odd memory cell array, comprising memory cells that correspond to odd column addresses; an odd column address decoder that corresponds to said odd memory cell array; an odd data-hold circuit for holding read data from said odd memory cell array; an even memory cell array, comprising memory cells that correspond to even column addresses; an even column address decoder that corresponds to said even memory cell array; and an even data-hold circuit for holding read data from said even memory cell array; wherein when the least significant bit in said first column address is odd, hold timing of said odd data-hold circuit is faster than hold timing of said even data-hold circuit.
Claim 3
Dependent Claim
38 words
The semiconductor memory device according to claim 1, wherein when the least significant bit in said first column address is even, said even data-hold circuit hold timing is roughly the same as said odd data-hold circuit hold timing.
Claim 4
Dependent Claim
80 words
The semiconductor memory device according to claims 1 or 2, comprises an arithmetic circuit, which supplies the second and third lower bits of said first column address as-is to said odd address decoder, and, when said least significant bit is even, supplies said second and third lower bits as-is to said even address decoder, and when said least significant bit is odd, increments said second and third lower bits and supplies the incremented lower bits to said even address decoder.
Claim 5
Dependent Claim
42 words
The semiconductor memory device according to claims 1 or 2, further comprising a data latch signal generator for generating odd data latch signals supplying said odd data-hold circuit hold timing, and even data latch signals supplying said even data-hold circuit hold timing.
Claim 6
Dependent Claim
62 words
The semiconductor memory device according to claims 1 or 2, wherein said odd data-hold circuit comprises an odd data bus amplifier for holding output data output from said odd memory cell array to a data bus; and said even data-hold circuit comprises an even data bus amplifier for holding output data output from said even memory cell array to the data bus.
Claim 7
Dependent Claim
102 words
The semiconductor memory device according to claim 5, further comprising: a first output latch circuit for latching, at a first clock, output data held by said even data-hold circuit when said least significant bit is even, and output data held by said odd data-hold circuit when said least significant bit is odd, respectively; and a second output latch circuit for latching, at a second clock slower than the first clock, output data held by said odd data-hold circuit when said least significant bit is even, and output data held by said even data-hold circuit when said least significant bit is odd, respectively.
Claim 8
Dependent Claim
220 words
A semiconductor memory device having a 2-bit pre-fetch function, which sequentially outputs first data of a memory cell that corresponds to an externally-supplied or internally-generated first column address, and a second data of a memory cell that corresponds to a second column address which increments said first column address, comprising: an odd memory cell array, comprising memory cells that correspond to odd column addresses; an odd column address decoder that corresponds to said odd memory cell array; an odd data-hold circuit for holding read data from said odd memory cell array; an odd even memory cell array, comprising memory cells that correspond to even column addresses; an even column address decoder that corresponds to said even memory cell array; an even data-hold circuit for holding read data from said even memory cell array; a predecoder for predecoding at least the two lower bits of said first column address; an odd address latch circuit for latching said predecoded signal and supplying the predecoded signal to said odd decoder; and an even address latch circuit for latching a predecoded first signal when said first column address is even, for latching second signal, which predecodes an address incremented at least said two lower bits when said first column address is odd, and for supplying said first or second signals to said even decoder.
Claim 9
Dependent Claim
220 words
A semiconductor memory device having a 2-bit pre-fetch function, which sequentially outputs first data of a memory cell that corresponds to an externally-supplied or internally-generated first column address, and a second data of a memory cell that corresponds to a second column address which increments said first column address, comprising: an odd memory cell array, comprising memory cells that correspond to odd column addresses; an odd column address decoder that corresponds to said odd memory cell array; an odd data-hold circuit for holding read data from said odd memory cell array; an odd even memory cell array, comprising memory cells that correspond to even column addresses; an even column address decoder that corresponds to said even memory cell array; an even data-hold circuit for holding read data from said even memory cell array; a predecoder for predecoding at least the two lower bits of said first column address; an odd address latch circuit for latching said predecoded signal and supplying the predecoded signal to said odd decoder; and an even address latch circuit for latching a predecoded first signal when said first column address is even, for latching second signal, which predecodes an address incremented at least said two lower bits when said first column address is odd, and for supplying said first or second signals to said even decoder.
Claim 10
Dependent Claim
30 words
The semiconductor memory device according to claim 7, wherein when said first column address is odd, said even address latch circuit latches a second signal that shifts said first signal.
Claim 11
Dependent Claim
41 words
The semiconductor memory device according to claims 7 or 8, wherein hold timing of said even data-hold circuit is roughly the same as hold timing of said odd data-hold circuit regardless of whether said first column address is even or odd.
Claim 12
Dependent Claim
60 words
The semiconductor memory device according to claim 7, wherein said odd data-hold circuit comprises an odd data bus amplifier for holding output data output from said odd memory cell array to a data bus; and said even data-hold circuit comprises an even data bus amplifier for holding output data output from said even memory cell array to the data bus.
Claim 13
Dependent Claim
102 words
The semiconductor memory device according to claim 10, further comprising: a first output latch circuit for latching, at a first clock, output data held by said even data-hold circuit when said first column address is even, and output data held by said odd data-hold circuit when said first column address is odd, respectively; and a second output latch circuit for latching, at a second clock slower than the first clock, output data held by said odd data-hold circuit when said first column address is even, and output data held by said even data-hold circuit when said first column address is odd, respectively.
Claim 14
Dependent Claim
214 words
A semiconductor memory device having a 2-bit pre-fetch function, which sequentially outputs first data of a memory cell that corresponds to an externally-supplied or internally-generated first column address, and a second data of a memory cell that corresponds to a second column address which increments said first column address, comprising: an odd memory cell array, comprising memory cells that correspond to odd column addresses; an odd column address decoder that corresponds to said odd memory cell array; an odd data-hold circuit for holding read data from said odd memory cell array; an even memory cell array, comprising memory cells that correspond to even column addresses; an even column address decoder that corresponds to said even memory cell array; an even data-hold circuit for holding read data from said even memory cell array; an address latch including an odd address latch circuit for latching a first signal predecoded at least the lower two bits of said first column address, and for supplying the first signal to said odd decoder; and an even address latch circuit for latching said first signal when said first column address is even, for latching a second signal shifted from said first signal said first column address is odd, and for supplying said first or second signals to said even decoder.
Claim 15
Dependent Claim
214 words
A semiconductor memory device having a 2-bit pre-fetch function, which sequentially outputs first data of a memory cell that corresponds to an externally-supplied or internally-generated first column address, and a second data of a memory cell that corresponds to a second column address which increments said first column address, comprising: an odd memory cell array, comprising memory cells that correspond to odd column addresses; an odd column address decoder that corresponds to said odd memory cell array; an odd data-hold circuit for holding read data from said odd memory cell array; an even memory cell array, comprising memory cells that correspond to even column addresses; an even column address decoder that corresponds to said even memory cell array; an even data-hold circuit for holding read data from said even memory cell array; an address latch including an odd address latch circuit for latching a first signal predecoded at least the lower two bits of said first column address, and for supplying the first signal to said odd decoder; and an even address latch circuit for latching said first signal when said first column address is even, for latching a second signal shifted from said first signal said first column address is odd, and for supplying said first or second signals to said even decoder.
Claim 16
Dependent Claim
76 words
The semiconductor memory device according to claim 12, wherein said address latch further comprises an internal address counter for generating a first internal signal shifted the output of said odd address latch circuit; and said first internal signal is latched by said odd address latch circuit, and said first internal signal or a second internal signal shifted said first internal signal is latched by said even address latch circuit, in accordance with a burst mode signal.
References Cited (Backward Citations)
US5453957A
Cited
US5787047A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-08 | 2002-09-07 | 2003-03-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-08 | 2006-09-07 | 2007-03-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-08 | 2010-09-07 | 2011-03-09 | $7700.00 | Window Closed / Lapsed |