Abstract A method of providing isolation structure in a semiconductor device having a shallow trench with a rounded top corner is provided for preventing stress centralization as well as current leakage of a device. The method includes the steps of: (a) sequentially forming a pad oxide layer and a silicon nitride layer on a semiconductor substrate; (b) forming an opening in the silicon nitride layer by a first anisotropic etching process, so as to expose an area for forming a shallow trench; (c) performing a wet etching process to remove the pad oxide layer within the opening, the wet etching process removing a portion of the pad oxide layer extending from the opening and under the silicon nitride layer; (d) performing an isotropic etching process to form a hollow with a rounded top corner in the semiconductor substrate, wherein the rounded top corner is located under the silicon nitride layer; and (e) continuously etching the hollow by a second anisotropic etching process using the silicon nitride layer as a mask, thereby forming a shallow trench having a rounded top corner in the semiconductor substrate.
A method of fabricating isolation structure in a semiconductor integrated circuit device comprising the steps of: (a) sequentially forming a pad oxide layer and a silicon nitride layer on a semiconductor substrate; (b) forming an opening in said silicon nitride layer by a first anisotropic etching process so as to expose an area for forming a shallow trench; (c) performing a wet etching process to remove said pad oxide layer within said opening, said etching process removing a portion of said pad oxide layer extending from said opening and under said silicon nitride layer; (d) performing an isotropic etching process to form a hollow with a rounded top corner in said semiconductor substrate, wherein said top corner rounding is located under said silicon nitride layer; and (e) etching said hollow by a second anisotropic etching process using said silicon nitride layer as a mask, thereby forming a shallow trench having a rounded top corner in said semiconductor substrate.
Claim 2
Independent Claim
158 words
A method of fabricating isolation structure in a semiconductor integrated circuit device comprising the steps of: (a) sequentially forming a pad oxide layer and a silicon nitride layer on a semiconductor substrate; (b) forming an opening in said silicon nitride layer by a first anisotropic etching process so as to expose an area for forming a shallow trench; (c) performing a wet etching process to remove said pad oxide layer within said opening, said etching process removing a portion of said pad oxide layer extending from said opening and under said silicon nitride layer; (d) performing an isotropic etching process to form a hollow with a rounded top corner in said semiconductor substrate, wherein said top corner rounding is located under said silicon nitride layer; and (e) etching said hollow by a second anisotropic etching process using said silicon nitride layer as a mask, thereby forming a shallow trench having a rounded top corner in said semiconductor substrate.
Claim 3
Dependent Claim
28 words
The method recited in claim 1, wherein the etching process in step (c) is a wet etching process performed by utilizing hydrogen fluoride (HF) solution as an etchant.
Claim 4
Dependent Claim
28 words
The method recited in claim 1, wherein said pad oxide layer in step (c) is etched to a thickness in a range between 700 Å and 1000 Å.
Claim 5
Dependent Claim
28 words
The method recited in claim 1, wherein the isotropic etching process in step (d) is performed in a dry etcher by providing sulfur hexafluoride (SF 6 ) gas.
Claim 6
Dependent Claim
24 words
The method recited in claim 1, wherein the isotropic etching process in step (d) is performed by applying a plasma power of about 200W.
Claim 7
Dependent Claim
27 words
The method recited in claim 1, wherein the thickness of said silicon nitride layer in step (b) is in a range between 1500 Å and 2000 Å.