Method of fabricating a semiconductor memory device

Claim 1

A fabrication method of a semiconductor memory device comprising: a first step of forming a first plurality of elements and a second plurality of elements on a semiconductor substrate, said first plurality of elements being located in a memory cell area, and said second plurality of elements being located in a peripheral circuit area; a second step of forming a first interlayer insulating layer to cover said first and second plurality of elements over said entire substrate; said first interlayer insulating layer having a first plurality of penetrating holes located in said memory cell area and a second plurality of penetrating holes located in said peripheral circuit area; a third step of forming a first conductive layer on said first interlayer insulating layer, said first conductive layer being electrically connected to said first plurality of elements through said first plurality of penetrating holes in said memory cell area and said second plurality of elements through second plurality of penetrating holes in said peripheral circuit area, respectively; a fourth step of patterning said first conductive layer to thereby form lower electrodes of capacitors in said memory cell area and contact pads in said peripheral circuit area; said lower electrodes being electrically connected to said first plurality of elements through said first plurality of penetrating holes, respectively; and said contact pads being electrically connected to said second plurality of elements through said second plurality of penetrating holes, respectively; a fifth step of forming an insulating layer to cover said lower electrodes and said contact pads over the entire substrate; a sixth step of forming a second conductive layer on said insulating layer over said entire substrate; a seventh step is to pattern said insulating layer and said second conductive layer to thereby form dielectric layers and upper electrodes of said capacitors in said memory cell area and pad insulating layers and pad protection layers in said peripheral circuit area; an eighth step of forming a second interlayer insulating layer to cover said upper electrodes of said capacitors and said pad protection layers over said entire substrate; a ninth step of forming contact holes penetrating said pad insulating layers and said pad protection layers in said peripheral circuit area, thereby exposing said respective contact pads; and a tenth step of forming interconnection conductors contacted with and electrically connected to said contact pads through said corresponding contact holes, respectively.