Semiconductor memory device

Claim 2

A semiconductor memory device comprising: a memory cell including a capacitor with first and second electrodes and a MOS transistor having a first source/drain, a second source/drain, a floating body sandwiched by said first source/drain and said second source/drain, and a gate formed above said floating body, wherein said first source/drain is connected to said second electrode of said capacitor; and charge draining means for draining out charge accumulated in the body of said MOS transistor via said second source/drain while the MOS transistor is rendered at an off state.

Claim 3

The semiconductor memory device according to claim 1, further comprising a first bit-line connected to said second source/drain of said MOS transistor, wherein said charge draining means has body-refresh-potential supplying means for supplying a body-refresh-potential for draining said charge accumulated in the body of said MOS transistor to said first bit-line.

Claim 4

The semiconductor memory device according to claim 2, wherein said body-refresh-potential supplying means includes bit-line precharging means for setting said first bit-line at a bit-line precharge potential, and in a body-refresh operation, for setting said first bit-line at a body-refresh potential.

Claim 5

The semiconductor memory device according to claim 2, further comprising a second bit-line forming a pair of bit-lines in conjunction with said first bit-line, wherein said body-refresh-potential supplying means includes a sense-amplifier for amplifying a difference in potential developed between said first and second bit-lines, and in a body-refresh operation, for setting one of said first and second bit-lines at a body-refresh potential.

Claim 6

The semiconductor memory device according to claim 2, wherein the body-refresh potential is lower than an L level of said first bit-line in a normal operation.

Claim 7

The semiconductor memory device according to claim 5, wherein the L level of said first bit-line in said normal operation is higher than an L level supplied to said gate of said MOS transistor, and the body-refresh potential is the L level supplied to said gate of said MOS transistor.

Claim 8

The semiconductor memory device according to claim 1, wherein said semiconductor memory device further comprises a conductive region forming a capacitance between the body of said MOS transistor and said conductive region, and potential control means for changing the potential of said conductive region in a body-refresh operation.

Claim 9

The semiconductor memory device according to claim 7, wherein said conductive region includes the first electrode of said capacitor.

Claim 10

The semiconductor memory device according to claim 7, wherein said MOS transistor is formed on a semiconductor layer of an SOI substrate comprising a semiconductor substrate, an insulation layer formed on said semiconductor substrate, and said semiconductor layer formed on said insulation layer, and said conductive region includes said semiconductor substrate.

Claim 11

The semiconductor memory device according to claim 1, wherein said semiconductor memory device has a sleep mode in which a self-refresh operation is carried out at predetermined intervals, and in the sleep mode, charge accumulated in the body of said MOS transistor is drained out by said charge draining means.

Claim 12

A semiconductor memory device comprising: a plurality of memory cells each including a capacitor with first and second electrodes, a MOS transistor having a first source/drain, and a second source/drain, a floating body sandwiched by said first source/drain and said second source/drain, and a gate, wherein said first source/drain is connected to said second electrode of said capacitor; a plurality of bit-line pairs arranged to form a plurality of columns, wherein each of said bit-line pairs is connected to said second source/drains of said memory cells on one of said columns; a plurality of sense-amplifiers each connected to one of said bit-line pairs for amplifying a difference in potential developed in said bit-line pair, and in a body-refresh operation, for setting one of the bit-lines in said bit-line pair at a body-refresh potential while the MOS transistors connected to said one of bit lines are rendered at an off state to drain out charge accumulated in the floating bodies of said MOS transistors to said one of the bit-lines in said bit-line pair; an I/O-line pair; and a plurality of gate circuits each provided between one of said bit-line pairs and said I/Q-line pair, said plurality of gate circuits selectively connecting one of said bit line pairs and said I/O-line pair electrically, and in the body-refresh operation, said plurality of gate circuits electrically connecting a plural number of said bit-line pairs and said I/O-line pair.

Claim 13

A semiconductor memory device comprising: a plurality of memory cells each including a capacitor with first and second electrodes, a MOS transistor having a first source/drain, and a second source/drain, a floating body sandwiched by said first source/drain and said second source/drain, and a gate, wherein said first source/drain is connected to said second electrode of said capacitor; a plurality of bit-line pairs arranged to form a plurality of columns, wherein each of said bit-line pairs is connected to said second source/drains of said memory cells on one of said columns; a plurality of sense-amplifiers each connected to one of said bit-line pairs for amplifying a difference in potential developed in said bit-line pair, and in a body-refresh operation, for setting one of the bit-lines in said bit-line pair at a body-refresh potential while the MOS transistors connected to said one of bit lines are rendered at an off state to drain out charge accumulated in the floating bodies of said MOS transistors to said one of the bit-lines in said bit-line pair; an I/O-line pair; and a plurality of gate circuits each provided between one of said bit-line pairs and said I/Q-line pair, said plurality of gate circuits selectively connecting one of said bit line pairs and said I/O-line pair electrically, and in the body-refresh operation, said plurality of gate circuits electrically connecting a plural number of said bit-line pairs and said I/O-line pair.

Claim 14

The semiconductor memory device according to claim 11, wherein the body-refresh potential is lower than an L level of said bit-line in a normal operation.

Claim 15

The semiconductor memory device according to claim 12, wherein the L level of said bit-line in said normal operation is higher than an L level supplied to said gate of said MOS transistor, and the body-refresh potential is the L level supplied to said gate of said MOS transistor.

Claim 16

The semiconductor memory device according to claim 11, wherein said semiconductor memory device further comprises a conductive region forming a capacitance between each body of said MOS transistors and said conductive region, and potential control means for changing the potential of said conductive region in a body-refresh operation.

Claim 17

The semiconductor memory device according to claim 14, wherein said conductive region includes each first electrode of said capacitors.

Claim 18

The semiconductor memory device according to claim 14, wherein each of said MOS transistors is formed on a semiconductor layer of an SOI substrate comprising a semiconductor substrate, an insulation layer formed on said semiconductor substrate, and said semiconductor layer formed on said insulation layer, and said conductive region includes said semiconductor substrate.