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US5877049A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for forming advanced transistor structures with optimum short channel controls for high density/high performance integrated circuits

Assignee: GlobalFoundries Inc
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Filing: 1996-09-23
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Granted: 1999-03-02
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Expires: 2016-09-23
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Abstract

Abstract A novel MOS transistor structure for improving device scaling by improving short channel control includes a buried back gate beneath a channel region of the MOS transistor. A separate contact to a well that is electrically communicated to the buried back gate improves short channel controls without performance degradations. In a preferred embodiment, the back gate is grounded when turning the n-channel MOS transistor off. In alternate embodiments, the buried layer produces retrograde p wells. In some applications, multiple buried layers may be used, with one or more being planar. CMOS devices may have independent, multiple buried back gates.

Inventors

  • 👤 Yowjuang W. Liu
  • 👤 Kuang-Yeh Chang

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 15:25
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/611; H10D30/615; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/378; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859; Y; Y10; Y10S; Y10S257/00; Y10S257/901

Claims Analysis

Total Claims: 17
Claim 1
Independent Claim 143 words
A method for forming a semiconductor device, comprising the steps of: forming, coupled to a substrate having a first conductivity-type, a first active region and a second active region separated from each other by a channel region wherein a gate overlies said channel region, said active regions being a second conductivity-type; forming, in said substrate, a well region of said second conductivity isolated from said active regions by an isolation region; thereafter implanting dopants of said second conductivity-type into said substrate through said active regions, said gate, said isolation region and said well region to form a first deep implant region that underlies said channel region and is electrically communicated to said well region; implanting dopants of said second conductivity-type into said active regions and said well region; and thereafter annealing said substrate to produce a buried structure from said first implant region.
Claim 2
Independent Claim 143 words
A method for forming a semiconductor device, comprising the steps of: forming, coupled to a substrate having a first conductivity-type, a first active region and a second active region separated from each other by a channel region wherein a gate overlies said channel region, said active regions being a second conductivity-type; forming, in said substrate, a well region of said second conductivity isolated from said active regions by an isolation region; thereafter implanting dopants of said second conductivity-type into said substrate through said active regions, said gate, said isolation region and said well region to form a first deep implant region that underlies said channel region and is electrically communicated to said well region; implanting dopants of said second conductivity-type into said active regions and said well region; and thereafter annealing said substrate to produce a buried structure from said first implant region.
Claim 3
Dependent Claim 79 words
The semiconductor device forming method of claim 1, further comprising the step of: implanting, prior to said annealing step, dopants of said first conductivity-type into said substrate through said active regions, said gate, said isolation region and said well region to form a second deep implant region that underlies said channel region and is disposed between said first implant region and said channel region, and wherein; said annealing step produces a second buried structure from said second implant region.
Claim 4
Independent Claim 169 words
A method for forming a semiconductor device, comprising the steps of: forming, coupled to a substrate having a first conductivity-type, a first active region and a second active region separated from each other by a channel region wherein a gate overlies said channel region, said active regions being a second conductivity-type; forming, in said substrate, a well region of said second conductivity isolated from said active regions by an isolation region; thereafter forming an implant mask over said substrate, said implant mask having exposure regions overlying said active regions, said gate, said isolation region and said well region; implanting dopants of said second conductivity-type through said exposure regions of said implant mask to produce a first implant region that underlies said channel region and is electrically communicated to said well region implanting dopants of said second conductivity-type through said exposure regions of said implant mask into said active regions and said well region; and thereafter annealing said substrate to produce a buried structure from said first deep implant region.
Claim 5
Independent Claim 169 words
A method for forming a semiconductor device, comprising the steps of: forming, coupled to a substrate having a first conductivity-type, a first active region and a second active region separated from each other by a channel region wherein a gate overlies said channel region, said active regions being a second conductivity-type; forming, in said substrate, a well region of said second conductivity isolated from said active regions by an isolation region; thereafter forming an implant mask over said substrate, said implant mask having exposure regions overlying said active regions, said gate, said isolation region and said well region; implanting dopants of said second conductivity-type through said exposure regions of said implant mask to produce a first implant region that underlies said channel region and is electrically communicated to said well region implanting dopants of said second conductivity-type through said exposure regions of said implant mask into said active regions and said well region; and thereafter annealing said substrate to produce a buried structure from said first deep implant region.
Claim 6
Dependent Claim 35 words
The semiconductor device forming method of claim 3 wherein said first implant region implanting step comprises applying a implant having a dose in a dose range of about 1×10 13 to about 1×10 16 .
Claim 7
Dependent Claim 28 words
The semiconductor device forming method of claim 4 wherein said first implant region implanting step comprises applying said implant having said dose less than about 1×10 15 .
Claim 8
Dependent Claim 31 words
The semiconductor device forming method of claim 4 wherein said first implant region implanting step comprises implanting arsenic atoms having an energy range of about 750 keV to about 2250 keV.
Claim 9
Dependent Claim 31 words
The semiconductor device forming method of claim 4 wherein said first implant region implanting step comprises implanting phosphorous atoms having an energy range of about 350 keV to about 1200 keV.
Claim 10
Dependent Claim 27 words
The semiconductor device forming method of claim 4 further comprising the step of: forming contacts coupled to said active regions, said gate, and to said well region.
Claim 11
Dependent Claim 70 words
The semiconductor device forming method of claim 4 further comprising the step of: implanting, prior to said annealing step, dopants of said first conductivity-type through said exposure regions of said implant mask to produce a second implant region that underlies said channel region and is disposed between said first implant region and said channel region, and wherein; said annealing step produces a second buried structure from said second implant region.
Claim 12
Dependent Claim 38 words
The semiconductor device forming method of claim 9 wherein said second implant region implanting step comprises applying a second implant having a second dose in a second dose range of about 1×10 13 to about 1×10 15 .
Claim 13
Dependent Claim 35 words
The semiconductor device forming method of claim 10 wherein said second implant region implanting step comprises implanting boron (B 11 ) atoms having a second energy range of about 200 keV to about 700 keV.
Claim 14
Independent Claim 129 words
A method for forming a semiconductor device, comprising the steps of: implanting a buried layer implant in a substrate having a first conductivity-type, said buried layer having a second conductivity type; thereafter forming, coupled to said substrate, a first active region and a second active region overlying said implant separated from each other by a channel region wherein a gate overlies said channel region, said active regions being a second conductivity-type; forming, in said substrate, a well region of said second conductivity isolated from said active regions by an isolation region, said well region electrically communicated to said buried layer; thereafter implanting dopants of said second conductivity-type into said active regions and said well region; and thereafter annealing said substrate to produce a buried structure from said buried implant.
Claim 15
Independent Claim 129 words
A method for forming a semiconductor device, comprising the steps of: implanting a buried layer implant in a substrate having a first conductivity-type, said buried layer having a second conductivity type; thereafter forming, coupled to said substrate, a first active region and a second active region overlying said implant separated from each other by a channel region wherein a gate overlies said channel region, said active regions being a second conductivity-type; forming, in said substrate, a well region of said second conductivity isolated from said active regions by an isolation region, said well region electrically communicated to said buried layer; thereafter implanting dopants of said second conductivity-type into said active regions and said well region; and thereafter annealing said substrate to produce a buried structure from said buried implant.
Claim 16
Independent Claim 10 words
The method of 12 wherein said buried structure is planar.
Claim 17
Independent Claim 10 words
The method of 12 wherein said buried structure is planar.

References Cited (Backward Citations)

US4864377A Cited
US5247200A Cited
US5191401A Cited
US5489540A Cited
US5608253A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-03-01 2002-08-31 2003-03-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-03-01 2006-08-31 2007-03-02 $3760.00 Window Closed / Lapsed
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