Patent US5875131A successfully refreshed from Google Patents.
US5875131A
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US
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Presettable static ram with read/write controller
Assignee: Winbond Electronics Corp
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Filing: 1997-12-10
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Granted: 1999-02-23
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Expires: 2017-12-10
Abstract
Abstract An array of static random access memory (SRAM) cells is configured for presetting to a particular value without the need to write to each cell in the array. Address line controllers are provided which are responsive to preset, read, and write signals. If a write control signal is asserted, the address line controllers maintain an asserted state on their address lines, so that a subsequent read cycle will output the written memory cell contents. However, if the memory cells in the array have not been written to, the address line controllers deassert their address lines, and simultaneously enable preset setting cells, so that a subsequent read cycle will output the logic state of the setting cells, rather than the contents of the array memory cells.
Inventors
- 👤 Rong-Fuh Shyu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 16:13
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/20; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/418; G11C11/419
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
385 words
A presettable static random access memory (SRAM), comprising: an array of memory cells, arranged in m rows and n columns, each of said n columns having a corresponding set of data lines, a row address decoder, a number m of row controller circuits, responsive to said row address decoder, corresponding to said m rows of memory cells, for controlling access to said m corresponding rows of memory cells, a column address decoder, for switching the outputs of said corresponding sets of data lines to a common set of bit lines, and for outputting column address signals to said row controller circuits, an input output (IO) circuit connected between said bit lines and a data bus, for passing data from said data bus to said bit lines upon receipt of a write control signal, and for passing data from said bit lines to said data bus upon receipt of a read signal, an enabling circuit, for receiving an activating output signal from said row controller circuits, and for outputting an enabling signal when so activated, a number n of setting cell circuits, each of said setting cell circuits being connected to said data lines of a corresponding one of said n columns of memory cells, said n setting cell circuits for receiving said enabling signal, which enables each of said setting cell circuits to output a particular logic state value to said data lines of said corresponding column, wherein when any of said m row controller circuits senses a write signal on its corresponding row line of said memory cells, said row controller circuit maintains the asserted state of said corresponding row line of said memory cells, wherein a subsequent read cycle will cause the contents of said corresponding row line of said memory cells to be outputted on said data lines, and wherein when said m row controller circuits do not sense a write signal on any of their corresponding row lines of said memory cells, said row controller circuits force the deassertion of said corresponding row lines of said memory cells, and simultaneously cause said enabling circuit to output said enabling signal to said n setting cell circuits, wherein a subsequent read cycle will cause said n setting cell circuits to output a particular logic state on said data lines of said corresponding columns.
Claim 2
Dependent Claim
385 words
A presettable static random access memory (SRAM), comprising: an array of memory cells, arranged in m rows and n columns, each of said n columns having a corresponding set of data lines, a row address decoder, a number m of row controller circuits, responsive to said row address decoder, corresponding to said m rows of memory cells, for controlling access to said m corresponding rows of memory cells, a column address decoder, for switching the outputs of said corresponding sets of data lines to a common set of bit lines, and for outputting column address signals to said row controller circuits, an input output (IO) circuit connected between said bit lines and a data bus, for passing data from said data bus to said bit lines upon receipt of a write control signal, and for passing data from said bit lines to said data bus upon receipt of a read signal, an enabling circuit, for receiving an activating output signal from said row controller circuits, and for outputting an enabling signal when so activated, a number n of setting cell circuits, each of said setting cell circuits being connected to said data lines of a corresponding one of said n columns of memory cells, said n setting cell circuits for receiving said enabling signal, which enables each of said setting cell circuits to output a particular logic state value to said data lines of said corresponding column, wherein when any of said m row controller circuits senses a write signal on its corresponding row line of said memory cells, said row controller circuit maintains the asserted state of said corresponding row line of said memory cells, wherein a subsequent read cycle will cause the contents of said corresponding row line of said memory cells to be outputted on said data lines, and wherein when said m row controller circuits do not sense a write signal on any of their corresponding row lines of said memory cells, said row controller circuits force the deassertion of said corresponding row lines of said memory cells, and simultaneously cause said enabling circuit to output said enabling signal to said n setting cell circuits, wherein a subsequent read cycle will cause said n setting cell circuits to output a particular logic state on said data lines of said corresponding columns.
Claim 3
Dependent Claim
137 words
The presettable SRAM of claim 1 wherein each of said m row controller circuits comprises n storage cells, said n storage cells corresponding to said n memory cells in the corresponding row of said array of memory cells, wherein when any of said n memory cells in a row is written to by means of a write control signal, said corresponding storage cell is flagged by said write control signal, and said flagged storage cell causes said asserted state to be maintained on said corresponding row of said n memory cells, and wherein when none of said n memory cells in a row are written to, said corresponding storage cells will not be flagged by a write control signal, and said unflagged storage cells will force said deassertion of said corresponding row of said n memory cells.
Claim 4
Dependent Claim
29 words
The presettable SRAM of claim 1 wherein any of said n setting cell circuits may be configured to output a logic 0 to said corresponding set of data lines.
Claim 5
Dependent Claim
29 words
The presettable SRAM of claim 1 wherein any of said n setting cell circuits may be configured to output a logic 1 to said corresponding set of data lines.
Claim 6
Dependent Claim
46 words
The presettable SRAM of claim 1 wherein said enabling circuit forms a logic NOR circuit with the output circuits of said m row controller circuits, said output circuits being commonly connected at a node in order to input a single activating signal to said enabling circuit.
Claim 7
Dependent Claim
25 words
The presettable SRAM of claim 1 wherein each of said sets of data lines and bit lines incorporates a precharge cell for voltage level equalization.
Claim 8
Dependent Claim
361 words
A presettable static random access memory (SRAM), comprising: an array of memory cells, arranged in m rows and n columns, each of said n columns having a corresponding set of data lines, a column address decoder, a number n of column controller circuits, responsive to said column address decoder, corresponding to said n columns of memory cells, for controlling access to said corresponding columns of memory cells, and for switching the outputs of said corresponding sets of data lines to a common set of bit lines, a row address decoder, for accessing said m rows of memory cells, and for outputting row address signals to said column controller circuits, an input output (IO) circuit connected between said bit lines and a data bus, for passing data from said data bus to said bit lines upon receipt of a write control signal, and for passing data from said bit lines to said data bus upon receipt of a read signal, an enabling circuit, for receiving an activating output signal from said n column controller circuits, and for outputting an enabling signal when so activated, a single setting cell circuit connected to said bit lines, said setting cell circuit for receiving said enabling signal, which enables said setting cell circuit to output a particular logic state value to said bit lines, wherein when any of said n column controller circuits senses a write signal on its corresponding column line of said memory cells, said column controller circuit maintains the asserted state of said corresponding column line of said memory cells, wherein a subsequent read cycle will cause the contents of said corresponding column line of said memory cells to be outputted on said bit lines, and wherein when said n column controller circuits do not sense a write signal on any of their corresponding column lines of said memory cells, said column controller circuits force the deassertion of said corresponding column lines of said memory cells, and simultaneously cause said enabling circuit to output said enabling signal to said setting cell circuit, wherein a subsequent read cycle will cause said setting cell circuit to output a particular logic state on said bit lines.
Claim 9
Dependent Claim
361 words
A presettable static random access memory (SRAM), comprising: an array of memory cells, arranged in m rows and n columns, each of said n columns having a corresponding set of data lines, a column address decoder, a number n of column controller circuits, responsive to said column address decoder, corresponding to said n columns of memory cells, for controlling access to said corresponding columns of memory cells, and for switching the outputs of said corresponding sets of data lines to a common set of bit lines, a row address decoder, for accessing said m rows of memory cells, and for outputting row address signals to said column controller circuits, an input output (IO) circuit connected between said bit lines and a data bus, for passing data from said data bus to said bit lines upon receipt of a write control signal, and for passing data from said bit lines to said data bus upon receipt of a read signal, an enabling circuit, for receiving an activating output signal from said n column controller circuits, and for outputting an enabling signal when so activated, a single setting cell circuit connected to said bit lines, said setting cell circuit for receiving said enabling signal, which enables said setting cell circuit to output a particular logic state value to said bit lines, wherein when any of said n column controller circuits senses a write signal on its corresponding column line of said memory cells, said column controller circuit maintains the asserted state of said corresponding column line of said memory cells, wherein a subsequent read cycle will cause the contents of said corresponding column line of said memory cells to be outputted on said bit lines, and wherein when said n column controller circuits do not sense a write signal on any of their corresponding column lines of said memory cells, said column controller circuits force the deassertion of said corresponding column lines of said memory cells, and simultaneously cause said enabling circuit to output said enabling signal to said setting cell circuit, wherein a subsequent read cycle will cause said setting cell circuit to output a particular logic state on said bit lines.
Claim 10
Dependent Claim
137 words
The presettable SRAM of claim 7 wherein each of said n column controller circuits comprises m storage cells, said m storage cells corresponding to said m memory cells in the corresponding column of said array of memory cells, wherein when any of said m memory cells in a column is written to by means of a write control signal, said corresponding storage cell is flagged by said write control signal, and said flagged storage cell causes said asserted state to be maintained on said corresponding column of said m memory cells, and wherein when none of said m memory cells in a column are written to, said corresponding storage cells will not be flagged by a write control signal, and said unflagged storage cells will force said deassertion of said corresponding column of said m memory cells.
Claim 11
Dependent Claim
23 words
The presettable SRAM of claim 7 wherein said setting cell circuit may be configured to output a logic 0 to said bit lines.
Claim 12
Dependent Claim
23 words
The presettable SRAM of claim 7 wherein said setting cell circuit may be configured to output a logic 1 to said bit lines.
Claim 13
Dependent Claim
46 words
The presettable SRAM of claim 7 wherein said enabling circuit forms a logic NOR circuit with the output circuits of said n column controller circuits, said output circuits being commonly connected at a node in order to input a single activating signal to said enabling circuit.
Claim 14
Dependent Claim
25 words
The presettable SRAM of claim 7 wherein each of said sets of data lines and bit lines incorporates a precharge cell for voltage level equalization.
Claim 15
Dependent Claim
314 words
A presettable static random access memory (SRAM), comprising: an array of memory cells, arranged in p rows and one column, said column having a corresponding set of data lines, an address decoder, a number p of row controller circuits, responsive to said address decoder, corresponding to said p rows of memory cells, for controlling access to said p corresponding rows of memory cells, an input output (IO) circuit connected between said data lines and a data bus, for passing data from said data bus to said data lines upon receipt of a write control signal, and for passing data from said data lines to said data bus upon receipt of a read signal, an enabling circuit, for receiving an activating output signal from said p row controller circuits, and for outputting an enabling signal when so activated, a setting cell circuit connected to said data lines, said setting cell circuit for receiving said enabling signal, which enables said setting cell circuit to output a particular logic state value to said data lines, wherein when any of said p row controller circuits senses a write signal on its corresponding row line of said memory cells, said row controller circuit maintains the asserted state of said corresponding row line of said memory cells, wherein a subsequent read cycle will cause the contents of said corresponding row line of said memory cells to be outputted on said data lines, and wherein when said p row controller circuits do not sense a write signal on any of their corresponding row lines of said memory cells, said row controller circuits force the deassertion of said corresponding row lines of said memory cells, and simultaneously cause said enabling circuit to output said enabling signal to said setting cell circuit, wherein a subsequent read cycle will cause said setting cell circuit to output a particular logic state on said data lines.
Claim 16
Dependent Claim
314 words
A presettable static random access memory (SRAM), comprising: an array of memory cells, arranged in p rows and one column, said column having a corresponding set of data lines, an address decoder, a number p of row controller circuits, responsive to said address decoder, corresponding to said p rows of memory cells, for controlling access to said p corresponding rows of memory cells, an input output (IO) circuit connected between said data lines and a data bus, for passing data from said data bus to said data lines upon receipt of a write control signal, and for passing data from said data lines to said data bus upon receipt of a read signal, an enabling circuit, for receiving an activating output signal from said p row controller circuits, and for outputting an enabling signal when so activated, a setting cell circuit connected to said data lines, said setting cell circuit for receiving said enabling signal, which enables said setting cell circuit to output a particular logic state value to said data lines, wherein when any of said p row controller circuits senses a write signal on its corresponding row line of said memory cells, said row controller circuit maintains the asserted state of said corresponding row line of said memory cells, wherein a subsequent read cycle will cause the contents of said corresponding row line of said memory cells to be outputted on said data lines, and wherein when said p row controller circuits do not sense a write signal on any of their corresponding row lines of said memory cells, said row controller circuits force the deassertion of said corresponding row lines of said memory cells, and simultaneously cause said enabling circuit to output said enabling signal to said setting cell circuit, wherein a subsequent read cycle will cause said setting cell circuit to output a particular logic state on said data lines.
Claim 17
Dependent Claim
128 words
The presettable SRAM of claim 13 wherein each of said p row controller circuits comprises a storage cell, said storage cell corresponding to said memory cell in the corresponding row of said array of memory cells, wherein when said memory cell in a row is written to by means of a write control signal, said corresponding storage cell is flagged by said write control signal, and said flagged storage cell causes said asserted state to be maintained on said corresponding row of said memory cell, and wherein when said memory cell in a row is not written to, said corresponding storage cell will not be flagged by a write control signal, and said unflagged storage cell will force said deassertion of said corresponding row of said memory cell.
Claim 18
Dependent Claim
23 words
The presettable SRAM of claim 13 wherein said setting cell circuit may be configured to output a logic 0 to said data lines.
Claim 19
Dependent Claim
23 words
The presettable SRAM of claim 13 wherein said setting cell circuit may be configured to output a logic 1 to said data lines.
Claim 20
Dependent Claim
46 words
The presettable SRAM of claim 13 wherein said enabling circuit forms a logic NOR circuit with the output circuits of said p row controller circuits, said output circuits being commonly connected at a node in order to input a single activating signal to said enabling circuit.
Claim 21
Dependent Claim
20 words
The presettable SRAM of claim 13 wherein said set of data lines incorporates a precharge cell for voltage level equalization.
Claim 22
Dependent Claim
297 words
A presentable static random access memory (SRAM), comprising: an array of memory cells, arranged in p rows and one column, said column having a corresponding set of data lines, an address decoder, a column controller circuit, responsive to said address decoder, for controlling access to said column of p memory cells, and for switching the outputs of said set of data lines to a set of bit lines, an input output (IO) circuit connected between said bit lines and a data bus, for passing data from said data bus to said bit lines upon receipt of a write control signal, and for passing data from said bit lines to said data bus upon receipt of a read signal, an enabling circuit, for receiving an activating output signal from said column controller circuit, and for outputting an enabling signal when so activated, a setting cell circuit connected to said bit lines, said setting cell circuit for receiving said enabling signal, which enables said setting cell circuit to output a particular logic state value to said bit lines, wherein when said column controller circuit senses a write signal on said column line of said memory cells, said column controller circuit maintains the asserted state of said column line, wherein a subsequent read cycle will cause the contents of said column line memory cells to be outputted on said bit lines, and wherein when said column controller circuit does not sense a write signal on said column line of said memory cells, said column controller circuit forces the deassertion of said column line, and simultaneously causes said enabling circuit to output said enabling signal to said setting cell circuit, wherein a subsequent read cycle will cause said setting cell circuit to output a particular logic state on said bit lines.
Claim 23
Dependent Claim
297 words
A presentable static random access memory (SRAM), comprising: an array of memory cells, arranged in p rows and one column, said column having a corresponding set of data lines, an address decoder, a column controller circuit, responsive to said address decoder, for controlling access to said column of p memory cells, and for switching the outputs of said set of data lines to a set of bit lines, an input output (IO) circuit connected between said bit lines and a data bus, for passing data from said data bus to said bit lines upon receipt of a write control signal, and for passing data from said bit lines to said data bus upon receipt of a read signal, an enabling circuit, for receiving an activating output signal from said column controller circuit, and for outputting an enabling signal when so activated, a setting cell circuit connected to said bit lines, said setting cell circuit for receiving said enabling signal, which enables said setting cell circuit to output a particular logic state value to said bit lines, wherein when said column controller circuit senses a write signal on said column line of said memory cells, said column controller circuit maintains the asserted state of said column line, wherein a subsequent read cycle will cause the contents of said column line memory cells to be outputted on said bit lines, and wherein when said column controller circuit does not sense a write signal on said column line of said memory cells, said column controller circuit forces the deassertion of said column line, and simultaneously causes said enabling circuit to output said enabling signal to said setting cell circuit, wherein a subsequent read cycle will cause said setting cell circuit to output a particular logic state on said bit lines.
Claim 24
Dependent Claim
121 words
The presettable SRAM of claim 19 wherein said column controller circuit comprises p storage cells, said p storage cells corresponding to said p memory cells in said array of memory cells, wherein when any of said p memory cells are written to by means of a write control signal, said corresponding storage cell is flagged by said write control signal, and said flagged storage cell causes said asserted state to be maintained on said column of said p memory cells, and wherein when none of said memory cells are written to, said corresponding storage cells will not be flagged by a write control signal, and said unflagged storage cells will force said deassertion of said column of said p memory cells.
Claim 25
Dependent Claim
23 words
The presettable SRAM of claim 19 wherein said setting cell circuit may be configured to output a logic 0 to said bit lines.
Claim 26
Dependent Claim
23 words
The presettable SRAM of claim 19 wherein said setting cell circuit may be configured to output a logic 1 to said bit lines.
Claim 27
Dependent Claim
28 words
The presentable SRAM of claim 19 wherein each of said set of data lines and said set of bit lines incorporates a precharge cell for voltage level equalization.
Claim 28
Independent Claim
91 words
A method of presetting a SRAM array without writing a preset value into each memory cell in said array, comprising the steps of: presetting a desired output state in setting cells, sensing the occurrence of a write signal to said memory cells, setting a write flag to denote said occurrence of said write signal, if said write flag is set, outputting the contents of said memory cells at a subsequent read cycle, if said write flag is not set, outputting the contents of said setting cells at a subsequent read cycle.
Claim 29
Independent Claim
91 words
A method of presetting a SRAM array without writing a preset value into each memory cell in said array, comprising the steps of: presetting a desired output state in setting cells, sensing the occurrence of a write signal to said memory cells, setting a write flag to denote said occurrence of said write signal, if said write flag is set, outputting the contents of said memory cells at a subsequent read cycle, if said write flag is not set, outputting the contents of said setting cells at a subsequent read cycle.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-02-22 | 2002-08-24 | 2003-02-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-22 | 2006-08-24 | 2007-02-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-22 | 2010-08-24 | 2011-02-23 | $7700.00 | Window Closed / Lapsed |