Abstract The invention provides an integrated systolic architecture which can perform both forward and inverse Discrete Wavelet Transforms with a minimum of complexity. A plurality of processing cells, each having an adder and a multiplier, are coupled to a set of multiplexers and delay elements to selectively receive a single input datastream in the forward DWT mode and two datastreams in the inverse DWT mode. In the forward DWT mode, the integrated architecture decomposes the input datastream into two output sequences--a high frequency sub-band output and a low frequency sub-band output. In the inverse DWT mode, the integrated architecture reconstructs the original input sequence by outputting even terms and odd terms on alternating clock cycles. As a result, the architecture can achieve 100% utilization and is suitable to be implemented in VLSI circuitry.
A systolic array for computing a forward Discrete Wavelet Transform of an input datastream, said array comprising: a plurality of processing cells, each cell computing an intermediate output x and an intermediate output y, said output x a function of low-pass digital filter coefficients, said output y a function of high-pass digital filter coefficients; an adder and controller coupled to said plurality of processing cells selectively adding said outputs x to generate low-frequency sub-band outputs of said Discrete Wavelet Transform, said adder/controller selectively adding said output y to generate high-frequency sub-band outputs of said Discrete Wavelet Transform; and delay elements coupled to said processing cells selectively delaying values of said datastream to said processing cells to the Discrete Wavelet Transform.
Claim 2
Dependent Claim
120 words
A systolic array for computing a forward Discrete Wavelet Transform of an input datastream, said array comprising: a plurality of processing cells, each cell computing an intermediate output x and an intermediate output y, said output x a function of low-pass digital filter coefficients, said output y a function of high-pass digital filter coefficients; an adder and controller coupled to said plurality of processing cells selectively adding said outputs x to generate low-frequency sub-band outputs of said Discrete Wavelet Transform, said adder/controller selectively adding said output y to generate high-frequency sub-band outputs of said Discrete Wavelet Transform; and delay elements coupled to said processing cells selectively delaying values of said datastream to said processing cells to the Discrete Wavelet Transform.
Claim 3
Dependent Claim
36 words
A systolic array according to claim 1 wherein each of said high-pass filter coefficients and said low-pass filter coefficients are symmetric, said symmetry reducing the number of processing cells required to compute said Discrete Wavelet Transform.
Claim 4
Dependent Claim
37 words
A systolic array according to claim 1 wherein each processing cell receives propagated input, each said cell adding said propagated input and values of said input datastream, each said cell multiplying the sum by said filter coefficients.
Claim 5
Dependent Claim
18 words
A systolic array according to claim 3, wherein each cell is composed of an adder and a multiplier.
Claim 6
Dependent Claim
17 words
A systolic array according to claim 1, wherein said digital filter coefficients are biorthogonal spline filter coefficients.