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US5875104A
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Operating switching power converters in a phased power sharing array
Assignee: VLT Corp
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Filing: 1997-06-26
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Granted: 1999-02-23
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Expires: 2017-06-26
Abstract
Abstract A method and apparatus for operating quantized power converters in a phase staggered power sharing array is disclosed. The number, N, of active converters in the array is automatically determined. The converter operating at the highest frequency is determined and awarded driver status. The system operating frequency is set to approximately N times the highest converter operating frequency and synchronous phase staggered timing signals are sent to the remaining converters. A method and apparatus for detecting faults and automatically reconfiguring the array are disclosed.
Inventors
- 👤 Jay Prager
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 07:02
CPC Classifications
H; H02; H02J; H02J1/00; H02J1/10; H02J1/102
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
126 words
A power sharing converter array comprising a plurality of quantized switching power converters having inputs connected to a power source and having outputs connected to a load; control circuitry including a timing circuit, a status circuit, and output circuitry; said timing circuit having inputs connected to receive converter operating cycle information from said converters; said status circuit having inputs connected to receive status signals from said converters and an output connected to said timing circuit for providing a tally of converters meeting predetermined criteria; said output circuitry connected to said timing circuitry for sending synchronizing signals to said converters; said control circuitry automatically determining the number, N, of converters in said array, and generating said synchronizing signals for operating said converters in a phase-staggered synchronized array.
Claim 2
Dependent Claim
126 words
A power sharing converter array comprising a plurality of quantized switching power converters having inputs connected to a power source and having outputs connected to a load; control circuitry including a timing circuit, a status circuit, and output circuitry; said timing circuit having inputs connected to receive converter operating cycle information from said converters; said status circuit having inputs connected to receive status signals from said converters and an output connected to said timing circuit for providing a tally of converters meeting predetermined criteria; said output circuitry connected to said timing circuitry for sending synchronizing signals to said converters; said control circuitry automatically determining the number, N, of converters in said array, and generating said synchronizing signals for operating said converters in a phase-staggered synchronized array.
Claim 3
Dependent Claim
32 words
The converter array of claim 1 wherein: the timing circuit determines the highest frequency of said converter operating cycles and generates a signal having a frequency approximately N times said highest frequency.
Claim 4
Dependent Claim
32 words
The converter array of claim 1 wherein said status circuit detects predetermined fault conditions and generates a signal to logically remove one or more of said converters from said phased-staggered synchronous array.
Claim 5
Dependent Claim
32 words
The converter array of claim 3 wherein said status circuit automatically adjusts said number, N, of converters in response to one or more of said converters being logically removed from said array.
Claim 6
Dependent Claim
25 words
The converter array of claim 4 wherein said status circuit ensures that a predetermined number of booster pulses are produced per booster per operating cycle.
Claim 7
Dependent Claim
47 words
The converter array of claim 1 wherein said timing circuit receives driver pulses from said converters and determines which one of said converters is operating at the highest frequency and awards driver status to one converter and awards booster status to the remaining converters in said array.
Claim 8
Dependent Claim
27 words
The converter array of claim 6 wherein said control circuit operates at a system frequency of approximately N times the frequency of driver pulses from said converters.
Claim 9
Dependent Claim
99 words
A control circuit for controlling power converters connected in a load sharing array, comprising: a timing circuit having inputs connected to receive converter operating cycle information from said converters; a status circuit having inputs connected to receive status signals from said converters and an output connected to said timing circuit for providing a tally of converters meeting predetermined criteria; output circuitry connected to said timing circuitry for sending synchronizing signals to said converters; said control circuitry automatically determining the number, N, of converters in said array, generating said synchronizing signals for operating said converters in a phase-staggered synchronized array.
Claim 10
Dependent Claim
99 words
A control circuit for controlling power converters connected in a load sharing array, comprising: a timing circuit having inputs connected to receive converter operating cycle information from said converters; a status circuit having inputs connected to receive status signals from said converters and an output connected to said timing circuit for providing a tally of converters meeting predetermined criteria; output circuitry connected to said timing circuitry for sending synchronizing signals to said converters; said control circuitry automatically determining the number, N, of converters in said array, generating said synchronizing signals for operating said converters in a phase-staggered synchronized array.
Claim 11
Dependent Claim
32 words
The control circuit of claim 8 wherein: the timing circuit determines the highest frequency of said converter operating cycles and generates a signal having a frequency approximately N times said highest frequency.
Claim 12
Dependent Claim
32 words
The control circuit of claim 9 wherein said status circuit detects predetermined fault conditions and generates a signal to logically remove one or more of said converters from said phased-staggered synchronous array.
Claim 13
Dependent Claim
32 words
The control circuit of claim 10 wherein said status circuit automatically adjusts said number, N, of converters in response to one or more of said converters being logically removed from said array.
Claim 14
Dependent Claim
25 words
The control circuit of claim 11 wherein said status circuit ensures that a predetermined number of booster pulses are produced per booster per operating cycle.
Claim 15
Dependent Claim
47 words
The control circuit of claim 8 wherein said timing circuit receives driver pulses from said converters and determines which one of said converters is operating at the highest frequency and awards driver status to one converter and awards booster status to the remaining converters in said array.
Claim 16
Dependent Claim
27 words
The control circuit of claim 13 wherein said control circuit operates at a system frequency of approximately N times the frequency of driver pulses from said converters.
Claim 17
Independent Claim
98 words
A method of operating power converters in a power sharing array comprising: receiving driver pulses from said converters; determining the number, N, of converters in said array; determining which one converter in said array is operating at the highest frequency, awarding driver converter status to said one converter, and awarding booster status to all converters in said array other than said driver converter; generating timing signals having a frequency of approximately N times the frequency of driver pulses; generating synchronization signals for said booster converters such that said booster converters are phase-staggered and synchronized with said driver converter.
Claim 18
Independent Claim
98 words
A method of operating power converters in a power sharing array comprising: receiving driver pulses from said converters; determining the number, N, of converters in said array; determining which one converter in said array is operating at the highest frequency, awarding driver converter status to said one converter, and awarding booster status to all converters in said array other than said driver converter; generating timing signals having a frequency of approximately N times the frequency of driver pulses; generating synchronization signals for said booster converters such that said booster converters are phase-staggered and synchronized with said driver converter.
Claim 19
Dependent Claim
27 words
The method of claim 15 wherein said determining the number process is carried out periodically to detect changes in said number N of converters in the array.
Claim 20
Dependent Claim
27 words
The method of claim 15 wherein said determining which one converter process is carried out periodically to allow said converters to change between driver and booster status.
Claim 21
Dependent Claim
27 words
The method of claim 15 further comprising monitoring said synchronization signals to ensure that a predetermined number of signals are produced per booster converter per operating cycle.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-22 | 2002-08-24 | 2003-02-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-22 | 2006-08-24 | 2007-02-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-22 | 2010-08-24 | 2011-02-23 | $7700.00 | Window Closed / Lapsed |