Three-dimensional graphics accelerator which implements multiple logical buses using common data lines for improved bus communication

Claim 2

A graphics accelerator with improved bus communications comprising: a command processor for receiving geometry input data and outputting initial geometric primitive data; a plurality of floating point processors for receiving said initial geometric primitive data from said command processor, wherein each of said plurality of floating point processors is configured to perform geometry processing operations on said initial geometric primitive data in order to produce modified geometric primitive data; a plurality of command/float buses, wherein each of said plurality of command/float buses couples said command processor to a respective one of said plurality of floating point processors; a frame buffer memory; one or more draw processors coupled to said frame buffer memory, wherein said one or more draw processors are configured to receive said modified geometric primitive data from said plurality of floating point processors, and wherein said one or more draw processors are configured to render pixel data corresponding to said modified geometric primitive data in the frame buffer memory; one or more float/draw buses for connecting said plurality of floating point processors to said one or more draw processors; wherein the graphics accelerator further includes one or more logical command/draw buses for transfer of data between said command processor and said one or more draw processors, wherein said one or more logical command/draw buses utilize at least a portion of said plurality of command/float buses and at least a portion of said one or more float/draw buses for said transfer of data between said command processor and said one or more draw processors; wherein at least a subset of said one or more floating point processors includes: floating point logic for performing said geometry processing operations; a first data path coupled between a respective one of said plurality of command/float buses and said floating point logic, wherein said first data path is usable for receiving said initial geometric primitive data from the command processor and providing said initial geometric primitive data to the floating point logic; a second data path coupled between said floating point logic and a respective one of said one or mote float/draw buses, wherein said second data path is usable for receiving said modified geometric primitive data from the floating point logic and providing said modified geometric primitive data to said one or more draw processors; a direct data path coupled to said respective one of said plurality of command/float buses and said respective one of said one or more float/draw buses, wherein said direct data path is usable for providing command data directly from said command processor to said one or more draw processors; and a multiplexer which receives an input from said second data path and said direct data path and which provides an output to said respective one of said one or more float/draw buses, wherein said multiplexer selects said second data path during transfers from said floating point processor to said one or more draw processors, and wherein said multiplexer selects said direct data path during transfers from said command processor to said one or more draw processors using said one or more logical command/draw buses.

Claim 3

The graphics accelerator of claim 1, wherein each of said plurality of floating point processors further includes an input buffer coupled to receive data from said respective one of said plurality of command/float buses, wherein said input buffer provides outputs to said direct data path and said floating point logic.

Claim 4

The graphics accelerator of claim 1, wherein at least a subset of said plurality of floating point processors perform operations during transfers on said one or more logical command/draw buses.

Claim 5

A graphics accelerator with improved bus communications comprising: a command and processor for receiving geometry input data and outputting initial geometric primitive data, wherein said command processor further includes: a plurality of command processor output buffers for providing output data to said plurality of command/float buses; a first data path for transferring data, wherein said first data path comprises a portion of said one or more logical command/draw buses; a multiplexer which receives an output from said plurality of command processor output buffers and which is coupled to receive data from said first data path; wherein said multiplexer selects said output from said plurality of command processor output buffers during transfers from said command processor to said plurality of floating point processors, wherein said multiplexer selects said output from said first data path during said transfer of data between said command processor and said one or more draw processors using said one or more logical command/draw buses; a plurality of floating point processors for receiving said initial geometric primitive data from said command processor, wherein each of said plurality of floating point processors is configured to perform geometry processing operations on said initial geometric primitive data in order to produce modified geometric primitive data; a plurality of command/float buses, wherein each of said plurality of command/float buses couples said command processor to a respective one of said plurality of floating point processors; a frame buffer memory; one or more draw processors coupled to said fame buffer memory, wherein said one or more draw processors are configured to receive said modified geometric primitive data from said plurality of floating point processors, and wherein said one or more draw processors are configured to render pixel data corresponding to said modified geometric primitive data in the frame buffer memory; one or more float/draw buses for connecting said plurality of floating point processors to said one or more draw processors; wherein the graphics accelerator further includes one or more logical command/draw buses for transfer of data between said command processor and said one or more draw processors, wherein said one or more logical command/draw buses utilize at least a portion of said plurality of command/float buses and at least a portion of said one or more float/draw buses for said transfer of data between said command processor and said one or more draw processors; wherein at least a subset of said one or more floating point processors includes: floating point logic for performing said geometry processing operations; a first data path coupled between a respective one of said plurality of command/float buses and said floating point logic, wherein said first data path is usable for receiving said initial geometric primitive data from the command processor and providing said initial geometric primitive data to the floating point logic; a second data path coupled between said floating point logic and a respective one of said one or more float/draw buses, wherein said second data path is usable for receiving said modified geometric primitive data from the floating point logic and providing said modified geometric primitive data to said one or more draw processors; a direct data path coupled to said respective one of said plurality of command/float buses and said respective one of said one or more float/draw buses wherein said direct data path is usable for providing command data directly from said command processor to said one or more draw processors.

Claim 6

A graphics accelerator with improved bus communications comprising: a command and processor for receiving geometry input data and outputting initial geometric primitive data, wherein said command processor further includes: a plurality of command processor output buffers for providing output data to said plurality of command/float buses; a first data path for transferring data, wherein said first data path comprises a portion of said one or more logical command/draw buses; a multiplexer which receives an output from said plurality of command processor output buffers and which is coupled to receive data from said first data path; wherein said multiplexer selects said output from said plurality of command processor output buffers during transfers from said command processor to said plurality of floating point processors, wherein said multiplexer selects said output from said first data path during said transfer of data between said command processor and said one or more draw processors using said one or more logical command/draw buses; a plurality of floating point processors for receiving said initial geometric primitive data from said command processor, wherein each of said plurality of floating point processors is configured to perform geometry processing operations on said initial geometric primitive data in order to produce modified geometric primitive data; a plurality of command/float buses, wherein each of said plurality of command/float buses couples said command processor to a respective one of said plurality of floating point processors; a frame buffer memory; one or more draw processors coupled to said fame buffer memory, wherein said one or more draw processors are configured to receive said modified geometric primitive data from said plurality of floating point processors, and wherein said one or more draw processors are configured to render pixel data corresponding to said modified geometric primitive data in the frame buffer memory; one or more float/draw buses for connecting said plurality of floating point processors to said one or more draw processors; wherein the graphics accelerator further includes one or more logical command/draw buses for transfer of data between said command processor and said one or more draw processors, wherein said one or more logical command/draw buses utilize at least a portion of said plurality of command/float buses and at least a portion of said one or more float/draw buses for said transfer of data between said command processor and said one or more draw processors; wherein at least a subset of said one or more floating point processors includes: floating point logic for performing said geometry processing operations; a first data path coupled between a respective one of said plurality of command/float buses and said floating point logic, wherein said first data path is usable for receiving said initial geometric primitive data from the command processor and providing said initial geometric primitive data to the floating point logic; a second data path coupled between said floating point logic and a respective one of said one or more float/draw buses, wherein said second data path is usable for receiving said modified geometric primitive data from the floating point logic and providing said modified geometric primitive data to said one or more draw processors; a direct data path coupled to said respective one of said plurality of command/float buses and said respective one of said one or more float/draw buses wherein said direct data path is usable for providing command data directly from said command processor to said one or more draw processors.

Claim 7

A graphics accelerator with improved bus communications comprising: a command processor for receiving geometry input data and outputting initial geometric primitive data; a plurality of floating point processors for receiving said initial geometric primitive data from said command processor, wherein each of said plurality of floating point processors is configured to perform geometry processing operations on said initial geometric primitive data in order to produce modified geometric primitive data; a plurality of command/float buses, wherein each of said plurality of command/float buses couples said command processor to a respective one of said plurality of floating point processors; a frame buffer memory; one or more draw processors coupled to said frame buffer memory, wherein said one or more draw processors are configured to receive said modified geometric primitive data from said plurality of floating point processors, and wherein said one or more draw processors are configured to render pixel data corresponding to said modified geometric primitive data in the frame buffer memory; one or more float/draw buses for connecting said plurality of floating point processors to said one or more draw processors, wherein the graphics accelerator further includes one or more logical command/draw buses for transfer of data between said command processor and said one or more draw processors, wherein said one or more logical command/draw buses utilize at least a portion of said plurality of command/float buses and at least a portion of said one or more float/draw buses for said transfer of data between said command processor and said one or more draw processors; wherein at least a subset of said one or more floating point processors includes: floating point logic for performing said geometry processing operations; a first data path coupled between a respective one of said plurality of command/float buses and said floating point logic, wherein said first data path is usable for receiving said initial geometric primitive data from the command processor and providing said initial geometric primitive data to the floating point logic; a second data path coupled between said floating point logic and a respective one of said one or more float/draw buses, wherein said second data path is usable for receiving said modified geometric primitive data from the floating point logic and providing said modified geometric primitive data to said one or more draw processors; a direct data path coupled to said respective one of said plurality of command/float buses and said respective one of said one or more float/draw buses, wherein said direct data path is usable for providing command data directly from said command processor to said one or more draw processors; wherein at least a subset of said plurality of command/float buses are utilized in said one or more logical command/draw buses; wherein each of said subset of said plurality of command/float buses has a first bus size, wherein each of said float/draw buses has a second bus size greater than said first bus size; wherein said graphics accelerator includes additional data lines for each of said subset of said plurality of command/float buses utilized in said one or more logical command/draw buses, wherein said additional data lines are used exclusively for said transfer of data between said command processor and said one or more draw processors on said one or more logical command/draw buses; wherein said additional data lines are used in conjunction with said subset of said plurality of command/float buses to provide a combined data path having said second bus size for each of said subset of said plurality of command/float buses.

Claim 8

A graphics accelerator with improved bus communications comprising: a command processor for receiving geometry input data and outputting initial geometric primitive data; a plurality of floating point processors for receiving said initial geometric primitive data from said command processor, wherein each of said plurality of floating point processors is configured to perform geometry processing operations on said initial geometric primitive data in order to produce modified geometric primitive data; a plurality of command/float buses, wherein each of said plurality of command/float buses couples said command processor to a respective one of said plurality of floating point processors; a frame buffer memory; one or more draw processors coupled to said frame buffer memory, wherein said one or more draw processors are configured to receive said modified geometric primitive data from said plurality of floating point processors, and wherein said one or more draw processors are configured to render pixel data corresponding to said modified geometric primitive data in the frame buffer memory; one or more float/draw buses for connecting said plurality of floating point processors to said one or more draw processors, wherein the graphics accelerator further includes one or more logical command/draw buses for transfer of data between said command processor and said one or more draw processors, wherein said one or more logical command/draw buses utilize at least a portion of said plurality of command/float buses and at least a portion of said one or more float/draw buses for said transfer of data between said command processor and said one or more draw processors; wherein at least a subset of said one or more floating point processors includes: floating point logic for performing said geometry processing operations; a first data path coupled between a respective one of said plurality of command/float buses and said floating point logic, wherein said first data path is usable for receiving said initial geometric primitive data from the command processor and providing said initial geometric primitive data to the floating point logic; a second data path coupled between said floating point logic and a respective one of said one or more float/draw buses, wherein said second data path is usable for receiving said modified geometric primitive data from the floating point logic and providing said modified geometric primitive data to said one or more draw processors; a direct data path coupled to said respective one of said plurality of command/float buses and said respective one of said one or more float/draw buses, wherein said direct data path is usable for providing command data directly from said command processor to said one or more draw processors; wherein at least a subset of said plurality of command/float buses are utilized in said one or more logical command/draw buses; wherein each of said subset of said plurality of command/float buses has a first bus size, wherein each of said float/draw buses has a second bus size greater than said first bus size; wherein said graphics accelerator includes additional data lines for each of said subset of said plurality of command/float buses utilized in said one or more logical command/draw buses, wherein said additional data lines are used exclusively for said transfer of data between said command processor and said one or more draw processors on said one or more logical command/draw buses; wherein said additional data lines are used in conjunction with said subset of said plurality of command/float buses to provide a combined data path having said second bus size for each of said subset of said plurality of command/float buses.