US5872994A
Expired / Lapsed
US
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Flash memory incorporating microcomputer having on-board writing function
Assignee: Acacia Research Group LLC
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Filing: 1996-11-12
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Granted: 1999-02-16
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Expires: 2016-11-12
Abstract
Abstract In a microcomputer comprising internal buses, a serial communication interface, a flash memory, a RAM, a ROM for storing a writing program, an input/output port, a CPU, and a mode control unit for setting various operation modes and test modes in the microcomputer, a switching circuit is connected between the ROM and the internal buses and between the input/output port and the internal buses. The mode control unit operates the switching circuit in an emulation test mode so that the ROM is deactivated and the input/output port is activated. Then, the CPU reads a program from the serial communication interface and writes the program into the flash memory in accordance with a writing program from the input/output port.
Inventors
- 👤 Shin-ichiro Akiyama
- 👤 Sadahiro Yasuda
- 👤 Yuichi Iizuka
- 👤 Hiroaki Nishimoto
- 👤 Yuuichi Osada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 21:09
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1415; G06F11/1433; G06F12/00; G06F12/02; G06F12/08; G06F11/22; G06F15/00; G06F15/76; G06F15/78
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
142 words
A microcomputer comprising: internal buses; a serial communication interface connected to said internal buses; a flash memory connected to said internal buses; a RAM, connected to said internal buses, for storing temporary data; a ROM for storing a writing program; an input/output port; a CPU; a switching circuit connected between said ROM and said internal buses and between said input/output port and said internal buses; and a mode control unit, connected to said internal buses, said serial communication interface, said flash memory, said RAM, said ROM, said CPU and said switching circuit, for operating said switching circuit in an emulation test mode so that said ROM is deactivated and said input/output port is activated, said CPU reading a program from said serial communication interface and writing said program into said flash memory in accordance with a writing program from said input/output port.
Claim 2
Dependent Claim
142 words
A microcomputer comprising: internal buses; a serial communication interface connected to said internal buses; a flash memory connected to said internal buses; a RAM, connected to said internal buses, for storing temporary data; a ROM for storing a writing program; an input/output port; a CPU; a switching circuit connected between said ROM and said internal buses and between said input/output port and said internal buses; and a mode control unit, connected to said internal buses, said serial communication interface, said flash memory, said RAM, said ROM, said CPU and said switching circuit, for operating said switching circuit in an emulation test mode so that said ROM is deactivated and said input/output port is activated, said CPU reading a program from said serial communication interface and writing said program into said flash memory in accordance with a writing program from said input/output port.
Claim 3
Dependent Claim
49 words
The microcomputer as set forth in claim 1, wherein said CPU performs a writing verification operation, a flash erasing operation and an erasing verification operation upon said flash memory in accordance with a writing verification program, a flash erasing program and an erasing verification program via said input/output port.
Claim 4
Dependent Claim
24 words
The microcomputer as set forth in claim 1, wherein said CPU temporarily stores said program in said RAM before writing into said flash memory.
Claim 5
Dependent Claim
27 words
The microcomputer as set forth in claim 1, wherein said CPU temporarily stores said program in a buffer of said CPU before writing into said flash memory.
Claim 6
Dependent Claim
196 words
A microcomputer as set forth in claim 1, wherein said flash memory comprises a control circuit for generating control signals for a writing operation and a flash erasing operation in response to a write enable signal and an erase signal, one unit of said control circuit for generating one of said control signals comprising: a timing generating circuit for receiving one of said write enable signal and said erase signal to generate a start pulse in response to a clock signal; a counter, connected to said timing generating circuit, for receiving said start pulse to count pulses of said clock signal; a register for storing a value corresponding to one of a writing operation time and a flash erasing operation time, said value being variable; a comparator, connected to said counter and said register, for comparing a value of said counter with the value of said register to generate a stop pulse when the value of said counter reaches the value of said register; and a pulse generating circuit, connected to said timing generating circuit and said comparator, for generating a corresponding one of said control signals defined by said start pulse and said stop pulse.
Claim 7
Dependent Claim
49 words
The microcomputer as set forth in claim 5, wherein the one unit of said control circuit further comprises a frequency detecting circuit, connected to said register, for detecting a frequency of said clock signal, a value corresponding to the frequency of said clock signal being set in said register.
Claim 8
Dependent Claim
90 words
The microcomputer as set forth in claim 6, wherein the one unit of said control circuit further comprises: a determination circuit, connected to said frequency detecting circuit, for determining whether or not the value corresponding to the frequency of said clock signal is larger than a maximum value of said register; means, connected to said determination circuit and said comparator, for delaying said stop pulse for a certain time period, when the value corresponding to the frequency of said clock signal is larger than the maximum value of said register.
Claim 9
Dependent Claim
94 words
The microcomputer as set forth in claim 6, wherein the one unit of said control circuit further comprises: a determination circuit, connected to said frequency detecting circuit, for determining whether or not the value corresponding to the frequency of said clock signal is larger than a maximum value of said register; and a pulse eliminating circuit, connected to said determination circuit and said counter, for eliminating a part of pulses of said clock signal, when the value corresponding to the frequency of said clock signal is larger than the maximum value of said register.
Claim 10
Independent Claim
194 words
A method for testing a microcomputer including: internal buses; a serial communication interface connected to said internal buses; a flash memory connected to said internal buses; a RAM, connected to said internal buses, for storing temporary data; a ROM for storing a writing program; an input/output port; a CPU; a switching circuit connected between said ROM and said internal buses and between said input/output port and said internal buses; a mode control unit, connected to said internal buses, said serial communication interface, said flash memory, said RAM, said ROM, said CPU and said switching circuit, for operating said switching circuit in an emulation test mode so that said ROM is deactivated and said input/output port is activated, said method comprising the steps of: connecting an emulation memory for storing said writing program to said input/output port, said emulation memory having the same address space as said ROM; connecting an emulation test data source for storing a program to said serial communication interface; and reading said program from said emulation test data source and writing said program into said flash memory in accordance with said writing program stored in said emulation memory by said CPU.
Claim 11
Independent Claim
194 words
A method for testing a microcomputer including: internal buses; a serial communication interface connected to said internal buses; a flash memory connected to said internal buses; a RAM, connected to said internal buses, for storing temporary data; a ROM for storing a writing program; an input/output port; a CPU; a switching circuit connected between said ROM and said internal buses and between said input/output port and said internal buses; a mode control unit, connected to said internal buses, said serial communication interface, said flash memory, said RAM, said ROM, said CPU and said switching circuit, for operating said switching circuit in an emulation test mode so that said ROM is deactivated and said input/output port is activated, said method comprising the steps of: connecting an emulation memory for storing said writing program to said input/output port, said emulation memory having the same address space as said ROM; connecting an emulation test data source for storing a program to said serial communication interface; and reading said program from said emulation test data source and writing said program into said flash memory in accordance with said writing program stored in said emulation memory by said CPU.
Claim 12
Dependent Claim
52 words
The method as set forth in claim 9, further comprising performing a writing verification operation, a flash erasing operation and an erasing verification operation upon said flash memory in accordance with a writing verification program, a flash erasing program and an erasing verification program stored in said emulation memory by said CPU.
Claim 13
Dependent Claim
97 words
A microcomputer comprising: internal buses; a serial communication interface connected to said internal buses; a flash memory connected to said internal buses; a RAM, connected to said internal buses, for-storing a writing program; a CPU; and a mode control unit, connected to said internal buses, said serial communication interface, said flash memory, said RAM, an input/output port and said CPU, for setting an on-board writing mode in said microcomputer, said CPU reading a program from said serial communication interface and writing said program into said flash memory in accordance with a writing program stored in said RAM.
Claim 14
Dependent Claim
97 words
A microcomputer comprising: internal buses; a serial communication interface connected to said internal buses; a flash memory connected to said internal buses; a RAM, connected to said internal buses, for-storing a writing program; a CPU; and a mode control unit, connected to said internal buses, said serial communication interface, said flash memory, said RAM, an input/output port and said CPU, for setting an on-board writing mode in said microcomputer, said CPU reading a program from said serial communication interface and writing said program into said flash memory in accordance with a writing program stored in said RAM.
Claim 15
Dependent Claim
40 words
The microcomputer as set forth in claim 11, wherein an area of said RAM for storing said writing program comprises flip-flop type cells each having two resistances and two cross-coupled transistors, one of said resistances being different from the other.
Claim 16
Dependent Claim
196 words
A microcomputer as set forth in claim 11, wherein said flash memory comprises a control circuit for generating control signals for a writing operation and a flash erasing operation in response to a write enable signal and an erase signal, one unit of said control circuit for generating one of said control signals comprising: a timing generating circuit for receiving one of said write enable signal and said erase signal to generate a start pulse in response to a clock signal; a counter, connected to said timing generating circuit, for receiving said start pulse to count pulses of said clock signal; a register for storing a value corresponding to one of a writing operation time and a flash erasing operation time, said value being variable; a comparator, connected to said counter and said register, for comparing a value of said counter with the value of said register to generate a stop pulse when the value of said counter reaches the value of said register; and a pulse generating circuit, connected to said timing generating circuit and said comparator, for generating a corresponding one of said control signals defined by said start pulse and said stop pulse.
Claim 17
Dependent Claim
49 words
The microcomputer as set forth in claim 13, wherein the one unit of said control circuit further comprises a frequency detecting circuit, connected to said register, for detecting a frequency of said clock signal, a value corresponding to the frequency of said clock signal being set in said register.
Claim 18
Dependent Claim
90 words
The microcomputer as set forth in claim 14, wherein the one unit of said control circuit further comprises: a determination circuit, connected to said frequency detecting circuit, for determining whether or not the value corresponding to the frequency of said clock signal is larger than a maximum value of said register; means, connected to said determination circuit and said comparator, for delaying said stop pulse for a certain time period, when the value corresponding to the frequency of said clock signal is larger than the maximum value of said register.
Claim 19
Dependent Claim
94 words
The microcomputer as set forth in claim 14, wherein the one unit of said control circuit further comprises: a determination circuit, connected to said frequency detecting circuit, for determining whether or not the value corresponding to the frequency of said clock signal is larger than a maximum value of said register; and a pulse eliminating circuit, connected to said determination circuit and said counter, for eliminating a part of pulses of said clock signal, when the value corresponding to the frequency of said clock signal is larger than the maximum value of said register.
Claim 20
Dependent Claim
109 words
A microcomputer comprising: internal buses; a serial communication interface connected to said internal buses; a flash memory connected to said internal buses; a RAM, connected to said internal buses, for storing temporary data; a ROM for storing a writing program; an input/output port; a CPU; and a mode control unit, connected to said internal buses, said serial communication interface, said flash memory, said RAM, said ROM, said CPU and said switching circuit, for setting operation modes and testing modes in said microcomputer, said serial communication interface including a plurality of kinds of serial communication interface units, and a selector means for selecting one of said serial communication interface units.
Claim 21
Dependent Claim
109 words
A microcomputer comprising: internal buses; a serial communication interface connected to said internal buses; a flash memory connected to said internal buses; a RAM, connected to said internal buses, for storing temporary data; a ROM for storing a writing program; an input/output port; a CPU; and a mode control unit, connected to said internal buses, said serial communication interface, said flash memory, said RAM, said ROM, said CPU and said switching circuit, for setting operation modes and testing modes in said microcomputer, said serial communication interface including a plurality of kinds of serial communication interface units, and a selector means for selecting one of said serial communication interface units.
Claim 22
Dependent Claim
196 words
A microcomputer as set forth in claim 17, wherein said flash memory comprises a control circuit for generating control signals for a writing operation and a flash erasing operation in response to a write enable signal and an erase signal, one unit of said control circuit for generating one of said control signals comprising: a timing generating circuit for receiving one of said write enable signal and said erase signal to generate a start pulse in response to a clock signal; a counter, connected to said timing generating circuit, for receiving said start pulse to count pulses of said clock signal; a register for storing a value corresponding to one of a writing operation time and a flash erasing operation time, said value being variable; a comparator, connected to said counter and said register, for comparing a value of said counter with the value of said register to generate a stop pulse when the value of said counter reaches the value of said register; and a pulse generating circuit, connected to said timing generating circuit and said comparator, for generating a corresponding one of said control signals defined by said start pulse and said stop pulse.
Claim 23
Dependent Claim
49 words
The microcomputer as set forth in claim 18, wherein the one unit of said control circuit further comprises a frequency detecting circuit, connected to said register, for detecting a frequency of said clock signal, a value corresponding to the frequency of said clock signal being set in said register.
Claim 24
Dependent Claim
90 words
The microcomputer as set forth in claim 19, wherein the one unit of said control circuit further comprises: a determination circuit, connected to said frequency detecting circuit, for determining whether or not the value corresponding to the frequency of said clock signal is larger than a maximum value of said register; means, connected to said determination circuit and said comparator, for delaying said stop pulse for a certain time period, when the value corresponding to the frequency of said clock signal is larger than the maximum value of said register.
Claim 25
Dependent Claim
94 words
The microcomputer as set forth in claim 19, wherein the one unit of said control circuit further comprises: a determination circuit, connected to said frequency detecting circuit, for determining whether or not the value corresponding to the frequency of said clock signal is larger than a maximum value of said register; and a pulse eliminating circuit, connected to said determination circuit and said counter, for eliminating a part of pulses of said clock signal, when the value corresponding to the frequency of said clock signal is larger than the maximum value of said register.
Claim 26
Dependent Claim
161 words
A microcomputer comprising: internal buses; a serial communication interface connected to said internal buses; a flash memory connected to said internal buses; a RAM, connected to said internal buses, for storing temporary data; a ROM for storing a writing program; an input/output port; a CPU; a mode control unit, connected to said internal buses, said serial communication interface, said flash memory, said RAM, said ROM, said CPU and said switching circuit, for setting an on-board writing operation in said microcomputer, and a data reception time detector, connected to said internal buses and said CPU, for counting an interval time between pieces of said program propagating said internal buses, said CPU temporarily storing said program in one of said RAM and a buffer of said CPU before writing said flash memory, when said interval time is smaller than a certain value, said CPU directly writing said program into said flash memory, when said interval time is not smaller than said certain value.
Claim 27
Dependent Claim
161 words
A microcomputer comprising: internal buses; a serial communication interface connected to said internal buses; a flash memory connected to said internal buses; a RAM, connected to said internal buses, for storing temporary data; a ROM for storing a writing program; an input/output port; a CPU; a mode control unit, connected to said internal buses, said serial communication interface, said flash memory, said RAM, said ROM, said CPU and said switching circuit, for setting an on-board writing operation in said microcomputer, and a data reception time detector, connected to said internal buses and said CPU, for counting an interval time between pieces of said program propagating said internal buses, said CPU temporarily storing said program in one of said RAM and a buffer of said CPU before writing said flash memory, when said interval time is smaller than a certain value, said CPU directly writing said program into said flash memory, when said interval time is not smaller than said certain value.
Claim 28
Dependent Claim
196 words
A microcomputer as set forth in claim 22, wherein said flash memory comprises a control circuit for generating control signals for a writing operation and a flash erasing operation in response to a write enable signal and an erase signal, one unit of said control circuit for generating one of said control signals comprising: a timing generating circuit for receiving one of said write enable signal and said erase signal to generate a start pulse in response to a clock signal; a counter, connected to said timing generating circuit, for receiving said start pulse to count pulses of said clock signal; a register for storing a value corresponding to one of a writing operation time and a flash erasing operation time, said value being variable; a comparator, connected to said counter and said register, for comparing a value of said counter with the value of said register to generate a stop pulse when the value of said counter reaches the value of said register; and a pulse generating circuit, connected to said timing generating circuit and said comparator, for generating a corresponding one of said control signals defined by said start pulse and said stop pulse.
Claim 29
Dependent Claim
49 words
The microcomputer as set forth in claim 23, wherein the one unit of said control circuit further comprises a frequency detecting circuit, connected to said register, for detecting a frequency of said clock signal, a value corresponding to the frequency of said clock signal being set in said register.
Claim 30
Dependent Claim
90 words
The microcomputer as set forth in claim 24, wherein the one unit of said control circuit further comprises: a determination circuit, connected to said frequency detecting circuit, for determining whether or not the value corresponding to the frequency of said clock signal is larger than a maximum value of said register; means, connected to said determination circuit and said comparator, for delaying said stop pulse for a certain time period, when the value corresponding to the frequency of said clock signal is larger than the maximum value of said register.
Claim 31
Dependent Claim
94 words
The microcomputer as set forth in claim 24, wherein the one unit of said control circuit further comprises: a determination circuit, connected to said frequency detecting circuit, for determining whether or not the value corresponding to the frequency of said clock signal is larger than a maximum value of said register; and a pulse eliminating circuit, connected to said determination circuit and said counter, for eliminating a part of pulses of said clock signal, when the value corresponding to the frequency of said clock signal is larger than the maximum value of said register.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-15 | 2002-08-17 | 2003-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-15 | 2006-08-17 | 2007-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-15 | 2010-08-17 | 2011-02-16 | $7700.00 | Window Closed / Lapsed |