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US5872735A
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Electrically alterable non-volatile memory with N-bits per cell
Assignee: BTG International Inc
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Filing: 1997-08-15
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Granted: 1999-02-16
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Expires: 2017-08-15
Abstract
Abstract An electrically alterable, non-volatile memory cell has more than 2 memory states that can be programmed selectively. Programming of the cell is conducted by applying a plurality of programming signals having different characteristics to the cell. The programming signals include at least a first programming signal which programs the cell by a first increment and a subsequent programming signal which programs the cell by a second increment smaller than the first increment. As the cell is being programmed to a selected state, its programming status is verified independently of reference values bounding the memory states. For this purpose, a signal indicative of the programming status (e.g., the cell's bit line signal) is compared with a reference signal corresponding to the selected state but having a value different from the reference value or values bounding the selected state. The programming operation can thus be controlled without actually reading the memory state of the cell.
Inventors
- 👤 Gerald J. Banks
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:39
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C11/5642; G11C16/34; G11C16/3436; G11C16/3454; G11C16/3459; G11C16/14; G11C16/16; G11C16/32; G11C2211/00; G11C2211/56; G11C2211/562; G11C2211/5621; G11C2211/563; G11C2211/5634; G11C2211/564; G11C2211/5642; G11C7/00; G11C7/10; G11C7/1006
Claims Analysis
Total Claims: 58
Claim 1
Independent Claim
69 words
A method of programming an electrically alterable non-volatile memory cell having more than two memory states, comprising: applying a plurality of programming pulses to said memory cell, said plurality of programming pulses including at least a first programming pulse and a subsequent programming pulse having a smaller pulse width than said first programming pulse, so as to program said memory cell to a selected one of said memory states.
Claim 2
Independent Claim
69 words
A method of programming an electrically alterable non-volatile memory cell having more than two memory states, comprising: applying a plurality of programming pulses to said memory cell, said plurality of programming pulses including at least a first programming pulse and a subsequent programming pulse having a smaller pulse width than said first programming pulse, so as to program said memory cell to a selected one of said memory states.
Claim 3
Dependent Claim
19 words
A method according to claim 1, further comprising verifying the programming status of said memory cell during said applying.
Claim 4
Dependent Claim
17 words
A method according to claim 2, wherein said verifying is performed in association with individual programming pulses.
Claim 5
Dependent Claim
22 words
A method according to claim 1, further comprising verifying the programming status of said memory cell after application of each programming pulse.
Claim 6
Dependent Claim
29 words
A method according to claim 2, wherein said verifying includes comparing a bit line signal of said memory cell to a reference signal corresponding to the selected memory state.
Claim 7
Dependent Claim
52 words
A method according to claim 5, wherein said comparing further includes selecting said reference signal from a plurality of reference signals selectively applicable to a comparator, each reference signal corresponding to a different one of said memory states, and applying the selected reference signal and the bit line signal to said comparator.
Claim 8
Dependent Claim
37 words
A method according to claim 5, wherein each memory state is bounded by one or more reference values, and said reference signal has a value different from the reference value or values bounding the selected memory state.
Claim 9
Independent Claim
47 words
A method of programming an electrically alterable non-volatile memory cell having more than two memory states, comprising: applying a plurality of programming pulses having successively decreasing pulse widths to said memory cell, so as to program said memory cell to a selected one of said memory states.
Claim 10
Independent Claim
47 words
A method of programming an electrically alterable non-volatile memory cell having more than two memory states, comprising: applying a plurality of programming pulses having successively decreasing pulse widths to said memory cell, so as to program said memory cell to a selected one of said memory states.
Claim 11
Dependent Claim
19 words
A method according to claim 8, further comprising verifying the programming status of said memory cell during said applying.
Claim 12
Dependent Claim
17 words
A method according to claim 9, wherein said verifying is performed in association with individual programming pulses.
Claim 13
Dependent Claim
22 words
A method according to claim 8, further comprising verifying the programming status of said memory cell after application of each programming pulse.
Claim 14
Dependent Claim
29 words
A method according to claim 9, wherein said verifying includes comparing a bit line signal of said memory cell to a reference signal corresponding to the selected memory state.
Claim 15
Dependent Claim
52 words
A method according to claim 12, wherein said comparing further includes selecting said reference signal from a plurality of reference signals selectively applicable to a comparator, each reference signal corresponding to a different one of said memory states, and applying the selected reference signal and the bit line signal to said comparator.
Claim 16
Dependent Claim
37 words
A method according to claim 12, wherein each memory state is bounded by one or more reference values, and said reference signal has a value different from the reference value or values defining the selected memory state.
Claim 17
Dependent Claim
77 words
A programmable multi-level memory apparatus, comprising: an electrically alterable non-volatile memory cell having more than two memory states; and a programming pulse generating device which applies a plurality of programming pulses to said memory cell, said plurality of programming pulses including at least a first programming pulse and a subsequent programming pulse having a smaller pulse width than said first programming pulse, so as to program said memory cell to a selected one of said memory states.
Claim 18
Dependent Claim
77 words
A programmable multi-level memory apparatus, comprising: an electrically alterable non-volatile memory cell having more than two memory states; and a programming pulse generating device which applies a plurality of programming pulses to said memory cell, said plurality of programming pulses including at least a first programming pulse and a subsequent programming pulse having a smaller pulse width than said first programming pulse, so as to program said memory cell to a selected one of said memory states.
Claim 19
Dependent Claim
31 words
An apparatus according to claim 15, further comprising a verifying device which verifies a programming status of said memory cell during programming of said memory cell with said plurality of pulses.
Claim 20
Dependent Claim
24 words
An apparatus according to claim 16, wherein said verifying device verifies the programming status of said memory cell in association with individual programming pulses.
Claim 21
Dependent Claim
26 words
An apparatus according to claim 15, further comprising a verifying device which verifies a programming status of said memory cell after application of each programming pulse.
Claim 22
Dependent Claim
33 words
An apparatus according to claim 16, wherein said verifying device comprises a comparator which compares a bit line signal of said memory cell to a reference signal corresponding to the selected memory state.
Claim 23
Dependent Claim
37 words
An apparatus according to claim 19, wherein each memory state is bounded by one or more reference values, and said reference signal has a value different from the reference value or values bounding the selected memory state.
Claim 24
Dependent Claim
63 words
An apparatus according to claim 19, wherein said verifying device includes a reference signal selector which selectively outputs a plurality of reference signals to said comparator, each of said plurality of reference signals corresponding to a different one of said memory states, said reference signal selector selecting the reference signal to be output to said comparator in accordance with the selected memory state.
Claim 25
Dependent Claim
55 words
A programmable multi-level memory apparatus, comprising: an electrically alterable non-volatile memory cell having more than two memory states; and a programming pulse generating device which applies a plurality of programming pulses having successively decreasing pulse widths to said memory cell, so as to program said memory cell to a selected one of said memory states.
Claim 26
Dependent Claim
55 words
A programmable multi-level memory apparatus, comprising: an electrically alterable non-volatile memory cell having more than two memory states; and a programming pulse generating device which applies a plurality of programming pulses having successively decreasing pulse widths to said memory cell, so as to program said memory cell to a selected one of said memory states.
Claim 27
Dependent Claim
31 words
An apparatus according to claim 22, further comprising a verifying device which verifies a programming status of said memory cell during programming of said memory cell with said plurality of pulses.
Claim 28
Dependent Claim
24 words
An apparatus according to claim 23, wherein said verifying device verifies the programming status of said memory cell in association with individual programming pulses.
Claim 29
Dependent Claim
26 words
An apparatus according to claim 22, further comprising a verifying device which verifies a programming status of said memory cell after application of each programming pulse.
Claim 30
Dependent Claim
33 words
An apparatus according to claim 23, wherein said verifying device comprises a comparator which compares a bit line signal of said memory cell to a reference signal corresponding to the selected memory state.
Claim 31
Dependent Claim
36 words
An apparatus according to claim 26, wherein each memory state is bounded by one or more reference values, and said reference signal has a value different from the value or values bounding the selected memory state.
Claim 32
Dependent Claim
63 words
An apparatus according to claim 26, wherein said verifying device includes a reference signal selector which selectively outputs a plurality of reference signals to said comparator, each of said plurality of reference signals corresponding to a different one of said memory states, said reference signal selector selecting the reference signal to be output to said comparator in accordance with the selected memory state.
Claim 33
Dependent Claim
72 words
A programming method for an electrically alterable non-volatile memory cell having more than two memory states, said method comprising: performing a programming operation of said memory cell; and controlling said programming operation so as to program said memory cell to a selected one of said memory states without reading the memory state of said memory cell, said controlling including verifying the programming status of said memory cell as it is being programmed.
Claim 34
Dependent Claim
72 words
A programming method for an electrically alterable non-volatile memory cell having more than two memory states, said method comprising: performing a programming operation of said memory cell; and controlling said programming operation so as to program said memory cell to a selected one of said memory states without reading the memory state of said memory cell, said controlling including verifying the programming status of said memory cell as it is being programmed.
Claim 35
Dependent Claim
30 words
A programming method according to claim 29, wherein said verifying includes comparing a bit line signal of said memory cell to a reference signal corresponding to the selected memory state.
Claim 36
Dependent Claim
108 words
A programming method for an electrically alterable non-volatile memory cell having more than two memory states, each of said memory states being bounded by one or more reference values, said method comprising: as said memory cell is being programmed to a selected one of said memory states, verifying the programming status of said memory cell independently of the reference values bounding the memory states, said verifying step including comparing a signal indicative of the programming status of said memory cell to a reference signal corresponding to the selected memory state, said reference signal having a value different from the reference value or values bounding the selected memory state.
Claim 37
Dependent Claim
108 words
A programming method for an electrically alterable non-volatile memory cell having more than two memory states, each of said memory states being bounded by one or more reference values, said method comprising: as said memory cell is being programmed to a selected one of said memory states, verifying the programming status of said memory cell independently of the reference values bounding the memory states, said verifying step including comparing a signal indicative of the programming status of said memory cell to a reference signal corresponding to the selected memory state, said reference signal having a value different from the reference value or values bounding the selected memory state.
Claim 38
Dependent Claim
28 words
A programming method according to claim 31, wherein the signal indicative of the programming status of said memory cell is a bit line signal of said memory cell.
Claim 39
Dependent Claim
67 words
A programming method for an electrically alterable non-volatile memory cell having more than two memory states, each of said memory states being bounded by one or more reference values, said method comprising: as said memory cell is being programmed to a selected one of said memory states, verifying the programming status of said memory cell without using the reference value or values bounding the selected memory state.
Claim 40
Dependent Claim
67 words
A programming method for an electrically alterable non-volatile memory cell having more than two memory states, each of said memory states being bounded by one or more reference values, said method comprising: as said memory cell is being programmed to a selected one of said memory states, verifying the programming status of said memory cell without using the reference value or values bounding the selected memory state.
Claim 41
Dependent Claim
51 words
A programming method according to claim 33, wherein said verifying includes comparing a signal indicative of the programming status of said memory cell to a reference signal corresponding to the selected memory state, said reference signal having a value different from the reference value or values bounding the selected memory state.
Claim 42
Dependent Claim
28 words
A programming method according to claim 34, wherein the signal indicative of the programming status of said memory cell is a bit line signal of said memory cell.
Claim 43
Dependent Claim
67 words
A programmable multi-level memory apparatus, comprising: an electrically alterable non-volatile memory cell having more than two memory states; and a programming device which performs a programming operation to program said memory cell to said memory states, selectively; said programming device including a verifying device which verifies the programming status of said memory cell without reading the memory state of said memory cell as it is being programmed.
Claim 44
Dependent Claim
67 words
A programmable multi-level memory apparatus, comprising: an electrically alterable non-volatile memory cell having more than two memory states; and a programming device which performs a programming operation to program said memory cell to said memory states, selectively; said programming device including a verifying device which verifies the programming status of said memory cell without reading the memory state of said memory cell as it is being programmed.
Claim 45
Dependent Claim
33 words
An apparatus according to claim 36, wherein said verifying device includes a comparator which compares a bit line signal of said memory cell to a reference signal corresponding to the selected memory state.
Claim 46
Dependent Claim
69 words
A programmable multi-level memory apparatus, comprising: an electrically alterable non-volatile memory cell having more than two memory states; and a programming device which performs a programming operation to program said memory cell to said memory states, selectively; said programming device including a verifying device which verifies the programming status of said memory cell, independently of the reference values bounding the memory states, as said memory cell is being programmed.
Claim 47
Dependent Claim
69 words
A programmable multi-level memory apparatus, comprising: an electrically alterable non-volatile memory cell having more than two memory states; and a programming device which performs a programming operation to program said memory cell to said memory states, selectively; said programming device including a verifying device which verifies the programming status of said memory cell, independently of the reference values bounding the memory states, as said memory cell is being programmed.
Claim 48
Dependent Claim
33 words
An apparatus according to claim 38, wherein said verifying device includes a comparator which compares a bit line signal of said memory cell to a reference signal corresponding to the selected memory state.
Claim 49
Dependent Claim
72 words
A programmable multi-level memory apparatus, comprising: an electrically alterable non-volatile memory cell having more than two memory states; and a programming device which performs a programming operation to program said memory cell to said memory states, selectively; said programming device including a verifying device which verifies the programming status of said memory cell, without using the reference value or values bounding the selected memory state, as said memory cell is being programmed.
Claim 50
Dependent Claim
72 words
A programmable multi-level memory apparatus, comprising: an electrically alterable non-volatile memory cell having more than two memory states; and a programming device which performs a programming operation to program said memory cell to said memory states, selectively; said programming device including a verifying device which verifies the programming status of said memory cell, without using the reference value or values bounding the selected memory state, as said memory cell is being programmed.
Claim 51
Dependent Claim
54 words
An apparatus according to claim 40, wherein said verifying device includes a comparator which compares a signal indicative of the programming status of said memory cell to a reference signal corresponding to the selected memory state, said reference signal having a value different from the reference value or values bounding the selected memory state.
Claim 52
Dependent Claim
27 words
An apparatus according to claim 41, wherein the signal indicative of the programming status of said memory cell is a bit line signal of said memory cell.
Claim 53
Dependent Claim
33 words
A method according to claim 1, wherein at least said first programming pulse and said subsequent programming pulse are applied to said memory cell before said memory cell reaches the selected memory state.
Claim 54
Dependent Claim
29 words
A method according to claim 1, wherein each programming pulse of said plurality subsequent to said first programming pulse is of smaller pulse width than said first programming pulse.
Claim 55
Dependent Claim
27 words
A method according to claim 8, wherein said programming pulses include programming pulses applied to said memory cell before said memory cell reaches the selected memory state.
Claim 56
Dependent Claim
33 words
An apparatus according to claim 15, wherein at least said first programming pulse and said subsequent programming pulse are applied to said memory cell before said memory cell reaches the selected memory state.
Claim 57
Dependent Claim
29 words
An apparatus according to claim 15, wherein each programming pulse of said plurality subsequent to said first programming pulse is of smaller pulse width than said first programming pulse.
Claim 58
Dependent Claim
27 words
An apparatus according to claim 22, wherein said programming pulses include programming pulses applied to said memory cell before said memory cell reaches the selected memory state.
References Cited (Backward Citations)
US4903236A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-15 | 2002-08-17 | 2003-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-15 | 2006-08-17 | 2007-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-15 | 2010-08-17 | 2011-02-16 | $7700.00 | Window Closed / Lapsed |