Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
289 words
A frequency synthesizer comprising: a phase locked loop including a voltage-controlled oscillator, a high frequency divider, a phase frequency comparator and a low-pass filter; a divisor controller circuit for supplying a divisor to the high frequency divider; and means for controlling the phase-locked loop so that a loop bandwidth of the phase locked loop is widened when an output frequency of the voltage-controlled oscillator is switched, and is narrowed when the switched output frequency is substantially stabilized after passing of a predetermined period, wherein the divisor controller circuit includes an accumulator having a phase adder and a phase register, wherein when the output frequency of the voltage-controlled oscillator is switched, the phase register is initialized, the phase adder adds its input data and the output of the phase register to make sum data that is given back to the phase register, the phase register inputs the data at the same time as changing of an output signal of the high frequency divider, the divisor controller circuit enlarges the divisor cyclically by incrementing the divisor only when the accumulator overflows, the high frequency divider divides the output signal of the voltage-controlled oscillator in accordance with the divisor, the phase frequency comparator generates a phase difference between an output signal of the high frequency divider and a reference signal, the phase difference signal is filtered by the low-pass filter and given to the voltage-controlled oscillator, which switches the output frequency to be equal to a product of the reference frequency and an average divisor of the high frequency divider, and wherein when the switched output frequency is substantially stabilized after passing of a predetermined period, the loop bandwidth is narrowed at the timing that the phase register becomes a predetermined value.
Claim 2
Dependent Claim
289 words
A frequency synthesizer comprising: a phase locked loop including a voltage-controlled oscillator, a high frequency divider, a phase frequency comparator and a low-pass filter; a divisor controller circuit for supplying a divisor to the high frequency divider; and means for controlling the phase-locked loop so that a loop bandwidth of the phase locked loop is widened when an output frequency of the voltage-controlled oscillator is switched, and is narrowed when the switched output frequency is substantially stabilized after passing of a predetermined period, wherein the divisor controller circuit includes an accumulator having a phase adder and a phase register, wherein when the output frequency of the voltage-controlled oscillator is switched, the phase register is initialized, the phase adder adds its input data and the output of the phase register to make sum data that is given back to the phase register, the phase register inputs the data at the same time as changing of an output signal of the high frequency divider, the divisor controller circuit enlarges the divisor cyclically by incrementing the divisor only when the accumulator overflows, the high frequency divider divides the output signal of the voltage-controlled oscillator in accordance with the divisor, the phase frequency comparator generates a phase difference between an output signal of the high frequency divider and a reference signal, the phase difference signal is filtered by the low-pass filter and given to the voltage-controlled oscillator, which switches the output frequency to be equal to a product of the reference frequency and an average divisor of the high frequency divider, and wherein when the switched output frequency is substantially stabilized after passing of a predetermined period, the loop bandwidth is narrowed at the timing that the phase register becomes a predetermined value.
Claim 3
Dependent Claim
23 words
The frequency synthesizer according to claim 1, wherein the accumulator operates using the output signal of the high frequency divider as a clock.
Claim 4
Dependent Claim
63 words
The frequency synthesizer according to claim 2, wherein the accumulator is made of n-bits, the accumulator switches the output frequency of the voltage-controlled oscillator fast with a wide loop width of the phase locked loop, and the loop bandwidth is narrowed when the value of the phase register becomes two raised to the power n-1 after the switched output frequency is substantially stabilized.
Claim 5
Dependent Claim
55 words
The frequency synthesizer according to claim 1, wherein the controlling means of the phase locked loop widens the passing band width of the low-pass filter for widening the loop width of the phase locked loop, and narrows the passing band width of the low-pass filter for narrowing the loop width of the phase locked loop.
Claim 6
Dependent Claim
126 words
The frequency synthesizer according to claim 1, further comprising a reference divider for dividing an output signal of a signal source to make a reference signal, wherein when the output frequency of the voltage-controlled oscillator is switched, the divisor of the high frequency divider is reduced to generate a cyclic change, the divisor of the reference divider is also reduced to raise the reference frequency, after the switched output frequency is substantially stabilized, the divisor of the high frequency divider is raised to a constant integer, and the divisor of the reference divider is enlarged to lower the reference frequency, so that the ratio of the average divisor of the high frequency divider and the divisor of the reference divider is constant before and after switching.
Claim 7
Dependent Claim
54 words
The frequency synthesizer according to claim 1, further comprising a timer circuit for maintaining the phase locked loop in a wide loop bandwidth for a predetermined period until the switched output frequency is substantially stabilized, and after passing of the predetermined period, narrowing the loop bandwidth when the phase register becomes a predetermined value.
Claim 8
Dependent Claim
48 words
The frequency synthesizer according to claim 1, wherein if a value of an input data of the accumulator is zero, the loop bandwidth of the phase locked loop is maintained wide for a predetermined period, and is narrowed at the first clock after passing of the predetermined period.