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Patent US5870435A successfully refreshed from Google Patents.
US5870435A
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Quantization/inverse quantization unit selectably accommodating multiple video encoding standards and including differential pulse code modulator
Assignee: Electronics and Telecommunications Research Institute
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Filing: 1997-04-25
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Granted: 1999-02-09
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Expires: 2017-04-25
Abstract
Abstract Disclosed is a quantization/inverse quantization circuit including a differential pulse code modulator (DPCM). Video CODEC standards (i.e., JPEG, H.261, H.263, MPEG-1, and MPEG-2) include various functions for an image compression and an image reconstruction. The conventional quantization/inverse quantization circuit has been designed to be fit for only one desired standard, so that the quantization/inverse quantization circuit used for one standard cannot be directly used for another standard. Accordingly, in relation to a difference between standards and required function therebetween in order to use the present invention in all video CODEC standards, the present invention discloses a quantization/inverse quantization circuit which can support all modes (i.e., a quantization mode in coding, an inverse quantization mode in decoding, and a reconstruction mode) by employing one quantization circuit as a quantization/inverse quantization circuit which can be used in all video CODEC standards.
Inventors
- 👤 Jang-Sik Choi
- 👤 Byoung-Ki Min
- 👤 Sang-Beom Kim
- 👤 Seung-Ku Hwang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 15:25
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/30; H03M7/3002; H03M7/3044; G; G06; G06T; G06T9/00; G06T9/005; H04; H04B; H04B14/00; H04B14/02; H04B14/06; H04N; H04N19/00; H04N19/60
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
179 words
A quantization/inverse quantization circuit having a differential pulse code modulator (DPCM) in a video coder-decoder (CODEC), comprising: an internal direct current (DC) processor which detects that a number `128` is converted to `255` in case of an inverse quantization of video CODEC standards H.261 and H.263 and then reconstructs an original number, or directly passes through other modes without any conversion, in order to quantize a discrete cosine transform (DCT) result in video CODEC standards JPEG, H.261, H.263, MPEG-1, and MPEG-2, to inverse quantize a differential pulse code modulation result or to inverse quantize again the quantized result; a Booth coded additive circuit which generates an input value of 3 bits necessary to a multiplier in order to perform a 3-bit multiplication; a Booth multiplier which actually performs a multiplication and a division in quantization/inverse quantization; a mismatch control circuit which is needed in said video CODEC standard MPEG-2; and a DPC path control circuit which obtains a difference between DC values of data blocks, and includes a selecting means for selecting an input according to a process mode.
Claim 2
Dependent Claim
179 words
A quantization/inverse quantization circuit having a differential pulse code modulator (DPCM) in a video coder-decoder (CODEC), comprising: an internal direct current (DC) processor which detects that a number `128` is converted to `255` in case of an inverse quantization of video CODEC standards H.261 and H.263 and then reconstructs an original number, or directly passes through other modes without any conversion, in order to quantize a discrete cosine transform (DCT) result in video CODEC standards JPEG, H.261, H.263, MPEG-1, and MPEG-2, to inverse quantize a differential pulse code modulation result or to inverse quantize again the quantized result; a Booth coded additive circuit which generates an input value of 3 bits necessary to a multiplier in order to perform a 3-bit multiplication; a Booth multiplier which actually performs a multiplication and a division in quantization/inverse quantization; a mismatch control circuit which is needed in said video CODEC standard MPEG-2; and a DPC path control circuit which obtains a difference between DC values of data blocks, and includes a selecting means for selecting an input according to a process mode.
Claim 3
Dependent Claim
157 words
The quantization/inverse quantization circuit including a DCPM in video CODEC as set forth in claim 1, in order to detect a decimal number `255` from input values in cases of said inverse quantization in said video CODEC standards H.261 and H.263 and then to convert `255` into `128`, wherein sdaid internal DC processor checks a mode signal H -- I -- DC indication said video CODEC standards H.261 and H.263, a sign bit being a most significant bit (MSB) of an input value, and the input value's 8 least significant bits (LSBs), and said input value is regarded as `255` when each of the aformentioned bits is `1`; said internal DC processor masks the 7 LSBs of said 8 LSBs with `0` by activating a 255 -- ACTIVE signal; and said internal DC processor directly passes said input value therthrough without any conversion in the case of modes other than said video CODEC standards H.261 and H.263.
Claim 4
Dependent Claim
135 words
The quantization/inverse quantization circuit including a DPCM in video CODEC as set forth in claim 1, wherein said mismatch control circuit performs an exclusive OR operation between an LSB of an inverse quantization result and a previous LSB through the last result value of a block, and said inverse quantization result is outputted, to discriminate wheter a sum of inverse quantization results of a block is an odd number or an even number in an inverse quantization mode of said video CODEC standard MPEG-2; and when said last result value is `10`, said mismatch control circuit performs an exclusive OR operation between a sum of LSBs and a current LSB in order to invert LSB of the last result, and converts a result of said exclusive OR operation into a current output LSB bit value.
Claim 5
Dependent Claim
155 words
The quantization/inverse quantization circuit including a DCPM in video CODEC as set forth in claim 1, wherein said quantization/inverse quantization circuit determines an output signal of a first selecting means selected by a MODE -- ENC signal from inputs consisting of an output IQ -- IN of said DPCM and a quantized output value IQ -- RECON; said quantization/inverse quantization circuit determines an output signal of a second selecting means selected by a Q -- INTRA signal from inputs consisting of a result of said first selecting means and a DCT result Q -- IN; said quantization/inverse quantization circuit reads a previous DC component at a position wherein a DC component value corresponding to said QINTRA signal is stored, and performs addition or subtraction using that DC component; and said quantization/inverse quantization circuit supports a third selecting means and said DPCM in quantization and inverse quantization modes, in order to store said DC component value.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-08 | 2002-08-10 | 2003-02-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-08 | 2006-08-10 | 2007-02-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-08 | 2010-08-10 | 2011-02-09 | $7700.00 | Window Closed / Lapsed |