US5870431A
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ROM-based finite impulse response filter for use in mobile telephone
Assignee: Qualcomm Inc
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Filing: 1996-06-27
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Granted: 1999-02-09
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Expires: 2016-06-27
Abstract
Abstract The finite impulse response (FIR) filter is implemented as a table using read-only memory (ROM). The FIR filter table stores a pre-calculated output filter value for each permissible combination of input values to be filtered. Streams of input values are successively shifted into the table and corresponding output values are successively output. In an exemplary implementation, the FIR filter is employed within a digital cellular telephone for use in smoothing a digital signal to be transmitted. The size of the required FIR filter table is minimized by exploiting constraints imposed upon the signal to be filtered and by exploiting linearity and symmetry within the filter itself. More specifically, the telephone employs a data burst randomizer to provide a data signal composed of sequences of null or 0 values and sequences of antipodal values (+1's and -1's). Hence, the permissible input combinations for the FIR filter include only patterns containing either all antipodal signals, all null signals, leading antipodal signals followed by trailing null signals, or leading null signals followed by trailing antipodal signals. The FIR filter look up is configured to exploit these limitations on the input streams yielding a look up table having relatively few entries. Method and apparatus implementations are disclosed.
Inventors
- 👤 Kenneth D. Easton
- 👤 Peter J. Black
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 15:03
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03H17/06; H03H17/0607
Claims Analysis
Total Claims: 45
Claim 1
Independent Claim
135 words
A finite impulse response (FIR) filter apparatus comprising: means for receiving an input signal stream having groups of consecutive non-null signals bracketed by groups of consecutive null signals; means for storing FIR filter output values, wherein the means for storing stores only FIR filter output values for each of a predetermined set of unique permissible input stream patterns, with the set of permissible input stream patterns including only patterns containing either leading non-null signals followed by trailing null signals, leading null signals followed by trailing non-null signals, all non-null signals or all null signals; and means for successively applying sequences of consecutive signals from the input signal stream to the means for storing to read out a sequence of output values corresponding to a filtered version of at least a portion of the input stream.
Claim 2
Dependent Claim
135 words
A finite impulse response (FIR) filter apparatus comprising: means for receiving an input signal stream having groups of consecutive non-null signals bracketed by groups of consecutive null signals; means for storing FIR filter output values, wherein the means for storing stores only FIR filter output values for each of a predetermined set of unique permissible input stream patterns, with the set of permissible input stream patterns including only patterns containing either leading non-null signals followed by trailing null signals, leading null signals followed by trailing non-null signals, all non-null signals or all null signals; and means for successively applying sequences of consecutive signals from the input signal stream to the means for storing to read out a sequence of output values corresponding to a filtered version of at least a portion of the input stream.
Claim 3
Dependent Claim
12 words
The apparatus of claim 1 wherein the non-null signals are antipodal signals.
Claim 4
Dependent Claim
13 words
The apparatus of claim 1 wherein the means for storing comprises a ROM.
Claim 5
Dependent Claim
19 words
The apparatus of claim 1 wherein the means for storing stores filter values corresponding to a symmetric FIR filter.
Claim 6
Dependent Claim
47 words
The apparatus of claim 1 wherein the permissible input stream patterns each include N signals and the groups of consecutive non-null signals each include at least N signals; and wherein sequences of N consecutive signals are applied to the means for storing, with N greater than 2.
Claim 7
Dependent Claim
147 words
A finite impulse response (FIR) filter apparatus for use in filtering an input signal stream, said filter apparatus comprising: a receiver receiving an input signal stream having groups of consecutive non-null signals bracketed by groups of consecutive null signals; a memory unit containing FIR filter output values, wherein the memory unit stores only FIR filter output values for each of a predetermined set of unique permissible input stream patterns, with the set of permissible input stream patterns including only patterns containing either leading non-null signals followed by trailing null signals, leading null signals followed by trailing non-null signals, all non-null signals or all null signals; and an input control unit for successively applying sequences of consecutive signals from the input signal stream to memory unit to read out a sequence of output values corresponding to a filtered version of at least a portion of the input stream.
Claim 8
Dependent Claim
147 words
A finite impulse response (FIR) filter apparatus for use in filtering an input signal stream, said filter apparatus comprising: a receiver receiving an input signal stream having groups of consecutive non-null signals bracketed by groups of consecutive null signals; a memory unit containing FIR filter output values, wherein the memory unit stores only FIR filter output values for each of a predetermined set of unique permissible input stream patterns, with the set of permissible input stream patterns including only patterns containing either leading non-null signals followed by trailing null signals, leading null signals followed by trailing non-null signals, all non-null signals or all null signals; and an input control unit for successively applying sequences of consecutive signals from the input signal stream to memory unit to read out a sequence of output values corresponding to a filtered version of at least a portion of the input stream.
Claim 9
Dependent Claim
12 words
The apparatus of claim 6 wherein the non-null signals are antipodal signals.
Claim 10
Dependent Claim
12 words
The apparatus of claim 6 wherein the memory unit comprises a ROM.
Claim 11
Dependent Claim
18 words
The apparatus of claim 6 wherein the memory unit stores filter values corresponding to a symmetric FIR filter.
Claim 12
Dependent Claim
46 words
The apparatus of claim 6 wherein the permissible input stream patterns each include N signals and the groups of consecutive non-null signals each include at least N signals; and wherein sequences of N consecutive signals are applied to the memory unit, with N greater than 2.
Claim 13
Independent Claim
139 words
A method for filtering an input signal stream, said method comprising the steps of: receiving an input signal stream to be filtered, said input signals stream having groups of consecutive non-null signals bracketed by groups of consecutive null signals; and successively applying sequences of consecutive signals from the input signal stream to a memory unit containing FIR filter output values to output a sequence of output values corresponding to a filtered version of at least a portion of the input stream, wherein the memory unit stores only FIR filter output values for each of a predetermined set of unique permissible input stream patterns, with the set of permissible input stream patterns including only patterns containing either leading non-null signals followed by trailing null signals, leading null signals followed by trailing non-null signals, all non-null signals or all null signals.
Claim 14
Independent Claim
139 words
A method for filtering an input signal stream, said method comprising the steps of: receiving an input signal stream to be filtered, said input signals stream having groups of consecutive non-null signals bracketed by groups of consecutive null signals; and successively applying sequences of consecutive signals from the input signal stream to a memory unit containing FIR filter output values to output a sequence of output values corresponding to a filtered version of at least a portion of the input stream, wherein the memory unit stores only FIR filter output values for each of a predetermined set of unique permissible input stream patterns, with the set of permissible input stream patterns including only patterns containing either leading non-null signals followed by trailing null signals, leading null signals followed by trailing non-null signals, all non-null signals or all null signals.
Claim 15
Dependent Claim
45 words
The method claim 11 wherein the permissible input stream patterns each include N signals and the groups of consecutive non-null signals each include at least N signals; and wherein sequences of N consecutive signals are applied to the memory unit, with N greater than 2.
Claim 16
Independent Claim
156 words
An apparatus for converting a digital signal into an analog signal, said apparatus comprising: means for receiving an input digital signal stream having groups of consecutive non-null signals bracketed by groups of consecutive null signals; means for storing digital FIR filter output values, wherein the means for storing stores only FIR filter output values for each of a predetermined set of unique permissible input stream patterns, with the set of permissible input stream patterns including only patterns containing either leading non-null signals followed by trailing null signals, leading null signals followed by trailing non-null signals, all non-null signals or all null signals; means for successively applying sequences of consecutive signals from the input digital signal stream to the means for storing to read out a sequence of digital FIR filter values corresponding to the input stream patterns; and digital to analog conversion means for converting the sequence of digital FIR filter values into an analog signal.
Claim 17
Independent Claim
156 words
An apparatus for converting a digital signal into an analog signal, said apparatus comprising: means for receiving an input digital signal stream having groups of consecutive non-null signals bracketed by groups of consecutive null signals; means for storing digital FIR filter output values, wherein the means for storing stores only FIR filter output values for each of a predetermined set of unique permissible input stream patterns, with the set of permissible input stream patterns including only patterns containing either leading non-null signals followed by trailing null signals, leading null signals followed by trailing non-null signals, all non-null signals or all null signals; means for successively applying sequences of consecutive signals from the input digital signal stream to the means for storing to read out a sequence of digital FIR filter values corresponding to the input stream patterns; and digital to analog conversion means for converting the sequence of digital FIR filter values into an analog signal.
Claim 18
Dependent Claim
13 words
The apparatus of claim 13 further comprising means for transmitting the analog signal.
Claim 19
Dependent Claim
18 words
The apparatus of claim 14 wherein the means for transmitting comprises a transmit unit of a cellular telephone.
Claim 20
Dependent Claim
22 words
The apparatus of claim 13 wherein the input digital signal stream is formatted in accordance with code division multiple access (CDMA) formats.
Claim 21
Dependent Claim
15 words
The apparatus of claim 13 wherein the means for storing comprises a read-only memory (ROM).
Claim 22
Dependent Claim
27 words
The apparatus of claim 14 wherein the means for transmitting comprises: means for transmitting an in-phase analog signal; and means for transmitting an quadrature phase analog signal.
Claim 23
Dependent Claim
36 words
The apparatus of claim 18 wherein the means for receiving the input digital signal stream comprises: means for receiving streams corresponding to an in-phase signal; and means for receiving streams corresponding to a quadrature phase signal.
Claim 24
Dependent Claim
44 words
The apparatus of claim 19 wherein the means for storing comprises: an in-phase memory unit for storing sets of digital values corresponding to permissible in-phase streams; and a quadrature phase memory unit for storing sets of digital values corresponding to permissible quadrature phase streams.
Claim 25
Dependent Claim
32 words
The apparatus of claim 13 further comprising: means for duplicating portions of the input digital signal stream; and means for selectively eliminating some of the duplicative portions within a predetermined time period.
Claim 26
Dependent Claim
20 words
The apparatus of claim 21 wherein each duplicative portion of the input digital signal stream comprises a power control group.
Claim 27
Dependent Claim
26 words
The apparatus of claim 21 wherein the means for selectively eliminating some of the duplicative portions of the input digital signal stream comprises a data-burst-randomizer (DBR).
Claim 28
Dependent Claim
12 words
The apparatus of claim 13 wherein the non-null signals are antipodal signals.
Claim 29
Dependent Claim
33 words
The apparatus of claim 13 wherein the digital FIR filter output values stored within the means for storing are representative of a linear, symmetric finite impulse representation of the permissible input stream patterns.
Claim 30
Dependent Claim
11 words
The apparatus of claim 13 implemented within an integrated circuit chip.
Claim 31
Dependent Claim
18 words
The apparatus of claim 13 wherein the means for storing stores separate values for four separate filter phases.
Claim 32
Dependent Claim
45 words
The apparatus of claim 27 wherein the means for storing stores partial sums representative of a 12-tap FIR filter employing forty-eight coefficients and wherein each value for each phase represents the sum of the product of six binary input values and six of the coefficients.
Claim 33
Independent Claim
143 words
A method for converting a digital signal into an analog signal, said method comprising the steps of: receiving an input digital signal stream having groups of consecutive non-null signals bracketed by groups of consecutive null signals; successively applying sequences of consecutive signals from the input digital signal stream to a memory unit containing digital FIR filter output values to read out a sequence of digital FIR filter values corresponding to the input stream patterns, wherein the memory unit contains only FIR filter output values for each of a predetermined set of unique permissible input stream patterns, with the set of permissible input stream patterns including only patterns containing either leading non-null signals followed by trailing null signals, leading null signals followed by trailing non-null signals, all non-null signals or all null signals; and converting the sequence of digital values into an analog signal.
Claim 34
Independent Claim
143 words
A method for converting a digital signal into an analog signal, said method comprising the steps of: receiving an input digital signal stream having groups of consecutive non-null signals bracketed by groups of consecutive null signals; successively applying sequences of consecutive signals from the input digital signal stream to a memory unit containing digital FIR filter output values to read out a sequence of digital FIR filter values corresponding to the input stream patterns, wherein the memory unit contains only FIR filter output values for each of a predetermined set of unique permissible input stream patterns, with the set of permissible input stream patterns including only patterns containing either leading non-null signals followed by trailing null signals, leading null signals followed by trailing non-null signals, all non-null signals or all null signals; and converting the sequence of digital values into an analog signal.
Claim 35
Dependent Claim
14 words
The method of claim 29 further comprising the step of transmitting the analog signal.
Claim 36
Dependent Claim
21 words
The method of claim 29 wherein the received digital signals are formatted in accordance with code division multiple access (CDMA) formats.
Claim 37
Dependent Claim
43 words
The method of claim 29 further comprising the steps of: duplicating portions of the input digital signal stream; and selectively eliminating some of the duplicative portions within a predetermined time period before successively applying the sequences of consecutive signals to the memory unit.
Claim 38
Dependent Claim
20 words
The method of claim 32 wherein each duplicative portion of the input digital signal stream comprises a power control group.
Claim 39
Dependent Claim
12 words
The method of claim 29 wherein the non-null signals are antipodal signals.
Claim 40
Independent Claim
193 words
An apparatus for converting a digital signal into an analog signal, said apparatus comprising: a receiver unit connected to an input line providing an input digital signal stream having groups of consecutive non-null signals bracketed by groups of consecutive null signals; a memory unit storing a table containing digital FIR filter output values, wherein the memory unit stores only FIR filter output values for each of a predetermined set of unique permissible input stream patterns, with the set of permissible input stream patterns including only patterns containing either leading non-null signals followed by trailing null signals, leading null signals followed by trailing non-null signals, all non-null signals or all null signals; a shift register, connected between the receiver unit and the memory unit, said shift register successively applying sequences of consecutive signals from the input digital signal stream to the memory unit to cause the memory unit to read out a sequence of digital FIR filter values corresponding to the input stream patterns; and a digital to analog converter connected to the memory unit, said digital to analog converter operating to convert the sequence of digital FIR filter values into an analog signal.
Claim 41
Independent Claim
193 words
An apparatus for converting a digital signal into an analog signal, said apparatus comprising: a receiver unit connected to an input line providing an input digital signal stream having groups of consecutive non-null signals bracketed by groups of consecutive null signals; a memory unit storing a table containing digital FIR filter output values, wherein the memory unit stores only FIR filter output values for each of a predetermined set of unique permissible input stream patterns, with the set of permissible input stream patterns including only patterns containing either leading non-null signals followed by trailing null signals, leading null signals followed by trailing non-null signals, all non-null signals or all null signals; a shift register, connected between the receiver unit and the memory unit, said shift register successively applying sequences of consecutive signals from the input digital signal stream to the memory unit to cause the memory unit to read out a sequence of digital FIR filter values corresponding to the input stream patterns; and a digital to analog converter connected to the memory unit, said digital to analog converter operating to convert the sequence of digital FIR filter values into an analog signal.
Claim 42
Dependent Claim
12 words
The apparatus of claim 35 wherein the non-null signals are antipodal signals.
Claim 43
Dependent Claim
17 words
The apparatus of claim 35 wherein the memory unit stores separate values for four separate filter phases.
Claim 44
Dependent Claim
44 words
The apparatus of claim 37 wherein the memory unit stores partial sums representative of a 12-tap FIR filter employing forty-eight coefficients and wherein each value for each phase represents the sum of the product of six binary input values and six of the coefficients.
Claim 45
Dependent Claim
47 words
The apparatus of claim 35 wherein the permissible input stream patterns each include N signals and the groups of consecutive non-null signals each include at least N signals; and wherein sequences of N consecutive signals are applied to the means for storing, with N greater than 2.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-08 | 2002-08-10 | 2003-02-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-08 | 2006-08-10 | 2007-02-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-08 | 2010-08-10 | 2011-02-09 | $7700.00 | Window Closed / Lapsed |