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US5870003A
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High frequency phase-locked loop circuit having reduced jitter
Assignee: International Business Machines Corp
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Filing: 1997-10-03
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Granted: 1999-02-09
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Expires: 2017-10-03
Abstract
Abstract A phase-locked loop circuit for providing external clock signals to a processor is disclosed. The phase-locked loop circuit includes a phase/frequency detector, a voltage-control oscillator, and two charge pumps. The phase/frequency detector receives an input reference signal and provides a first differential output and a second differential output. The voltage-controlled oscillator has a feed-forward current input and is utilized to generate an output clock signal, wherein the output clock signal is also utilized as a feedback signal for the phase/frequency detector. The first charge-pump, coupled between the phase/frequency detector and the voltage-controlled oscillator, receives the first and second differential outputs from the phase/frequency detector and provides a differential voltage control signal for the voltage-controlled oscillator. The second charge pump is utilized to produce a stable system response by increasing the loop dumping.
Inventors
- 👤 David William Boerstler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:24
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/089; H03L7/0891; H03L7/0895; H03L7/0896
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
88 words
A phase-locked loop circuit comprising: a phase/frequency detector for receiving an input reference signal, wherein said phase/frequency detector has a first output and a second output; a voltage-controlled oscillator with feedforward current input for generating an output clock signal, wherein said output clock signal is also utilized as a feedback signal for said phase/frequency detector; and a first charge-pump coupled between said phase/frequency detector and said voltage-controlled oscillator, wherein said first charge-pump receives said first and second outputs and generates two complementary control signals for said voltage-controlled oscillator.
Claim 2
Dependent Claim
88 words
A phase-locked loop circuit comprising: a phase/frequency detector for receiving an input reference signal, wherein said phase/frequency detector has a first output and a second output; a voltage-controlled oscillator with feedforward current input for generating an output clock signal, wherein said output clock signal is also utilized as a feedback signal for said phase/frequency detector; and a first charge-pump coupled between said phase/frequency detector and said voltage-controlled oscillator, wherein said first charge-pump receives said first and second outputs and generates two complementary control signals for said voltage-controlled oscillator.
Claim 3
Dependent Claim
46 words
The phase-locked loop circuit according to claim 1, wherein said circuit further includes a second charge-pump coupled between said phase/frequency detector and said voltage-control oscillator, wherein said second charge-pump receives said first and second outputs and generates a differential current feed-forward signal for said voltage-control oscillator.
Claim 4
Dependent Claim
20 words
The phase-locked loop circuit according to claim 1, wherein said two complementary control signals form a differential current control signal.
Claim 5
Dependent Claim
27 words
The phase-locked loop circuit according to claim 3, wherein said differential current control signal is integrated by a filter circuit to produce a differential voltage control signal.
Claim 6
Dependent Claim
17 words
The phase-locked loop circuit according to claim 4, wherein said filter circuit includes at least two capacitors.
Claim 7
Dependent Claim
28 words
The phase-locked loop circuit according to claim 1, wherein said circuit further includes a replica biasing circuit for providing a replica bias control voltage to said voltage-control oscillator.
Claim 8
Dependent Claim
118 words
A processor comprising: a processing unit; a memory cache coupled to said processing unit; a phase-locked loop circuit for provide a clock signal to said processor, wherein said phase-locked loop further includes a phase/frequency detector for receiving an input reference signal, wherein said phase/frequency detector has a first differential output and a second differential output; a voltage-controlled oscillator with feedforward current input for generating an output clock signal, wherein said output clock signal is also utilized as a feedback signal for said phase/frequency detector; and a first charge-pump coupled between said phase/frequency detector and said voltage-controlled oscillator, wherein said first charge-pump receives said first and second differential outputs and generates two complementary control signals for said voltage-controlled oscillator.
Claim 9
Dependent Claim
118 words
A processor comprising: a processing unit; a memory cache coupled to said processing unit; a phase-locked loop circuit for provide a clock signal to said processor, wherein said phase-locked loop further includes a phase/frequency detector for receiving an input reference signal, wherein said phase/frequency detector has a first differential output and a second differential output; a voltage-controlled oscillator with feedforward current input for generating an output clock signal, wherein said output clock signal is also utilized as a feedback signal for said phase/frequency detector; and a first charge-pump coupled between said phase/frequency detector and said voltage-controlled oscillator, wherein said first charge-pump receives said first and second differential outputs and generates two complementary control signals for said voltage-controlled oscillator.
Claim 10
Dependent Claim
46 words
The phase-locked loop circuit according to claim 7, wherein said circuit further includes a second charge-pump coupled between said phase/frequency detector and said voltage-control oscillator, wherein said second charge-pump receives said first and second outputs and generates a differential current feed-forward signal for said voltage-control oscillator.
Claim 11
Dependent Claim
20 words
The phase-locked loop circuit according to claim 7, wherein said two complementary control signals form a differential current control signal.
Claim 12
Dependent Claim
27 words
The phase-locked loop circuit according to claim 9, wherein said differential current control signal is integrated by a filter circuit to produce a differential voltage control signal.
Claim 13
Dependent Claim
17 words
The phase-locked loop circuit according to claim 10, wherein said filter circuit includes at least two capacitors.
Claim 14
Dependent Claim
28 words
The phase-locked loop circuit according to claim 7, wherein said circuit further includes a replica biasing circuit for providing a replica bias control voltage to said voltage-control oscillator.
References Cited (Backward Citations)
US5740213A
Cited
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