Open loop pre-amplifier for an electronic measuring system

Claim 2

An amplifier circuit for amplifying a pair of electric signals and having a process-independent gain, comprising: a differential common-source amplifier portion to which the pair of electric signals are input, the differential common-source amplifier portion comprising input transistors having a doping type; a load portion outputting a pair of amplified electric signals, the load portion comprising a pair of diode-connected transistors that are the same doping type as the input transistors; a current mirror portion connected between the differential, common-source amplifier portion and the load portion; and a common voltage supply portion connected to the load portion; wherein the process-independent gain of the amplifier circuit is independent of process variables of a process used to form the amplifier circuit.

Claim 3

The amplifier circuit of claim 1, wherein the differential, common-source amplifier portion and the load portion have transistors having a first doping type, and the current mirror has transistors having a second doping type.

Claim 4

The amplifier circuit of claim 2, wherein the common voltage supply portion also has transistors having the first doping type.

Claim 5

The amplifier circuit of claim 2, wherein the differential, common-source amplifier portion and the load portion each comprise PMOS transistors, and the current mirror comprises NMOS transistors.

Claim 6

The amplifier circuit of claim 4, wherein the common voltage supply portion comprises PMOS transistors.

Claim 7

The amplifier circuit of claim 1, wherein the differential common source amplifier portion comprises: a first P-type transistor, a first one of the pair of electric signals connected to a gate of the first P-type transistor; a second P-type transistor, a second one of the pair of electric signals connected to a gate of the second P-type transistor; and a current source connected to a source of each of the first and second P-type transistors; wherein a drain of each of the first and second P-type transistors is connected to the current mirror portion.

Claim 8

An amplifier circuit for amplifying a pair of electric signals and having a process-independent gain, comprising: a differential common-source amplifier portion to which the pair of electric signals are input, comprising: a first P-type transistor, a first one of the pair of electric signals connected to a gate of the first P-type transistor, a second P-type transistor, a second one of the pair of electric signals connected to a gate of the second P-type transistor, and a current source connected to a source of each of the first and second P-type transistors; a load portion outputting a pair of amplified electric signals; a current mirror portion connected between the differential, common-source amplifier portion and the load portion, comprising: a first N-type transistor, a gate and a drain of the first N-type transistor connected to the drain of the first P-type transistor and a source of the first N-type transistor connected to ground, a second N-type transistor, a gate and a drain of the second N-type transistor connected to the drain of the second P-type transistor and a source of the second N-type transistor connected to ground, a third N-type transistor, a gate of the third N-type transistor connected to the gate of the second N-type transistor and a source of the third N-type transistor connected to ground, and a fourth N-type transistor, a gate of the fourth N-type transistor connected to the gate of the first N-type transistor and a source of the fourth N-type transistor connected to ground; and a common voltage supply portion connected to the load portion; wherein: the process-independent gain of the amplifier circuit is independent of process variables of a process used to form the amplifier circuit, a drain of each of the first and second P-type transistors is connected to the current mirror portion, and a drain of each of the third and fourth N-type transistors are connected to the load portion.

Claim 9

An amplifier circuit for amplifying a pair of electric signals and having a process-independent gain, comprising: a differential common-source amplifier portion to which the pair of electric signals are input, comprising: a first P-type transistor, a first one of the pair of electric signals connected to a gate of the first P-type transistor, a second P-type transistor, a second one of the pair of electric signals connected to a gate of the second P-type transistor, and a current source connected to a source of each of the first and second P-type transistors; a load portion outputting a pair of amplified electric signals; a current mirror portion connected between the differential, common-source amplifier portion and the load portion, comprising: a first N-type transistor, a gate and a drain of the first N-type transistor connected to the drain of the first P-type transistor and a source of the first N-type transistor connected to ground, a second N-type transistor, a gate and a drain of the second N-type transistor connected to the drain of the second P-type transistor and a source of the second N-type transistor connected to ground, a third N-type transistor, a gate of the third N-type transistor connected to the gate of the second N-type transistor and a source of the third N-type transistor connected to ground, and a fourth N-type transistor, a gate of the fourth N-type transistor connected to the gate of the first N-type transistor and a source of the fourth N-type transistor connected to ground; and a common voltage supply portion connected to the load portion; wherein: the process-independent gain of the amplifier circuit is independent of process variables of a process used to form the amplifier circuit, a drain of each of the first and second P-type transistors is connected to the current mirror portion, and a drain of each of the third and fourth N-type transistors are connected to the load portion.

Claim 10

The amplifier circuit of claim 7, wherein the load portion comprises: a third P-type transistor, a gate and a drain of the third P-type transistor connected to the source of the third N-type transistor and outputting a first one of the pair of amplified electric circuits; and a fourth P-type transistor, a gate and a drain of the fourth P-type transistor connected to the source of the fourth N-type transistor and outputting a second one of the pair of amplified electric signals; wherein a source of each of the third and fourth P-type transistors is connected to the common voltage supply portion.

Claim 11

The amplifier circuit of claim 8, wherein the common voltage supply circuit comprises: a fifth P-type transistor, a source of the fifth P-type transistor connected to a voltage source and a drain of the fifth P-type transistor connected to the sources of the third and fourth P-type transistors; a sixth P-type transistor, a source of the sixth P-type transistor connected to the drain of the fifth P-type transistor; a second current source connected between ground and a gate and a drain of the sixth P-type transistor; a first controllable switch, a first pole of the first controllable switch connected to a gate of the fifth P-type transistor; a second controllable switch, a first pole of the second controllable switch connected to the gate and the drain of the sixth P-type transistor; a capacitor connected between the gate of the fifth P-type transistor and a second pole of the second controllable switch; a third controllable switch connected between a reference voltage and the second pole of the second controllable switch; a seventh P-type transistor, a source of the seventh P-type transistor connected to the voltage source, a gate and a drain of the seventh P-type transistor connected to a second pole of the first controllable switch; and a third current source connected between ground and the gate and drain of the seventh P-type transistor; wherein the first and third controllable switches are commonly controlled.

Claim 12

An amplifier circuit for amplifying a pair of electric signals and having a process-independent gain, comprising: a differential common-source amplifier portion to which the pair of electric signals are input; a load portion outputting a pair of amplified electric signals; a current mirror portion connected between the differential, common-source amplifier portion and the load portion; and a common voltage supply portion connected to the load portion, wherein: the process-independent gain of the amplifier circuit is independent of process variables of a process used to form the amplifier circuit, and the pair of electric signals are generated by a transducer circuit and the pair of amplified signals are input to a sample and hold circuit.

Claim 13

An amplifier circuit for amplifying a pair of electric signals and having a process-independent gain, comprising: a differential common-source amplifier portion to which the pair of electric signals are input; a load portion outputting a pair of amplified electric signals; a current mirror portion connected between the differential, common-source amplifier portion and the load portion; and a common voltage supply portion connected to the load portion, wherein: the process-independent gain of the amplifier circuit is independent of process variables of a process used to form the amplifier circuit, and the pair of electric signals are generated by a transducer circuit and the pair of amplified signals are input to a sample and hold circuit.

Claim 14

The amplifier circuit of claim 10, wherein the transducer circuit comprises an electronic position encoder.

Claim 15

The amplifier circuit of claim 11, wherein the transducer circuit further comprises a multiplexer connected between the electronic position encoder and the differential common source amplifier portion.

Claim 16

An amplifier circuit for amplifying a pair of electric signals, the amplifier circuit comprising a plurality of serially connected amplifier stages, the pair of electric signals connected to and input as a pair of signals by a first one of the plurality of stages, a pair of amplified output signals output by each stage input by each downstream stage of the plurality of stages as the pair of signals, a last stage of the plurality of stages outputting a pair of amplified output signals as the pair of amplified electric signals to a next circuit element, wherein each stage comprises: a differential, common-source amplifier portion to which the pair of signals are input; a load portion outputting the pair of amplified output signals; and a current mirror portion connected between the differential, common-source amplifier portion and the load portion; wherein a gain of each stage is independent of process variables of a process used to form the amplifier circuit.

Claim 17

An amplifier circuit for amplifying a pair of electric signals, the amplifier circuit comprising a plurality of serially connected amplifier stages, the pair of electric signals connected to and input as a pair of signals by a first one of the plurality of stages, a pair of amplified output signals output by each stage input by each downstream stage of the plurality of stages as the pair of signals, a last stage of the plurality of stages outputting a pair of amplified output signals as the pair of amplified electric signals to a next circuit element, wherein each stage comprises: a differential, common-source amplifier portion to which the pair of signals are input; a load portion outputting the pair of amplified output signals; and a current mirror portion connected between the differential, common-source amplifier portion and the load portion; wherein a gain of each stage is independent of process variables of a process used to form the amplifier circuit.

Claim 18

The amplifier circuit of claim 13, further comprising a common voltage supply circuit connected to each of the plurality of stages.

Claim 19

The amplifier circuit of claim 14, wherein the common voltage supply circuit comprises: a first P-type transistor, a source of the first P-type transistor connected to a voltage source and a drain of the first P-type transistor connected to the load portion; a second P-type transistor, a source of the second P-type transistor connected to the drain of the first P-type transistor; a first current source connected between ground and a gate and a drain of the second P-type transistor; a first controllable switch, a first pole of the first controllable switch connected to a gate of the first P-type transistor; a second controllable switch, a first pole of the second controllable switch connected to the gate and the drain of the second P-type transistor; a capacitor connected between the gate of the first P-type transistor and a second pole of the second controllable switch; a third controllable switch connected between a reference voltage and the second pole of the second controllable switch; a third P-type transistor, a source of the third P-type transistor connected to the voltage source, a gate and a drain of the third P-type transistor connected to a second pole of the first controllable switch; and a second current source connected between ground and the gate and drain of the third P-type transistor; wherein the first and third controllable switches are commonly controlled.

Claim 20

The amplifier circuit of claim 13, wherein each stage further comprises a separate common voltage supply circuit.

Claim 21

The amplifier circuit of claim 16, wherein the separate common voltage supply circuit of each stage comprises: a first P-type transistor, a source of the first P-type transistor connected to a voltage source and a drain of the first P-type transistor connected to the load portion; a second P-type transistor, a source of the second P-type transistor connected to the drain of the first P-type transistor; a first current source connected between ground and a gate and a drain of the second P-type transistor; a first controllable switch, a first pole of the first controllable switch connected to a gate of the first P-type transistor; a second controllable switch, a first pole of the second controllable switch connected to the gate and the drain of the second P-type transistor; a capacitor connected between the gate of the first P-type transistor and a second pole of the second controllable switch; a third controllable switch connected between a reference voltage and the second pole of the second controllable switch; a third P-type transistor, a source of the third P-type transistor connected to the voltage source, a gate and a drain of the third P-type transistor connected to a second pole of the first controllable switch; and a second current source connected between ground and the gate and drain of the third P-type transistor; wherein the first and third controllable switches are commonly controlled.

Claim 22

The amplifier circuit of claim 13, wherein the differential, common-source amplifier portion of each stage comprises: a first P-type transistor, a first one of the pair of signals connected to a gate of the first P-type transistor; a second P-type transistor, a second one of the pair of electric signals connected to a gate of the second P-type transistor; and a current source connected to a source of each of the first and second P-type transistors; wherein a drain of each of the first and second P-type transistors is connected to the current mirror portion.

Claim 23

The amplifier circuit of claim 18, wherein the current mirror portion of each stage comprises: a first N-type transistor, a gate and a source of the first N-type transistor connected to the drain of the first P-type transistor and a drain of the first N-type transistor connected to ground; a second N-type transistor, a gate and a source of the second N-type transistor connected to the drain of the second P-type transistor and a drain of the second N-type transistor connected to ground; a third N-type transistor, a gate of the third N-type transistor connected to the gate of the second N-type transistor and a drain of the third N-type transistor connected to ground; and a fourth N-type transistor, a gate of the fourth N-type transistor connected to the gate of the first N-type transistor and a drain of the fourth N-type transistor connected to ground; wherein a source of each of the third and fourth N-type transistors are connected to the load portion.

Claim 24

The amplifier circuit of claim 19, wherein the load portion of each stage comprises: a third P-type transistor, a gate and a drain of the third P-type transistor connected to the source of the third N-type transistor and outputting a first one of the pair of amplified electric circuits; and a fourth P-type transistor, a gate and a drain of the fourth P-type transistor connected to the source of the fourth N-type transistor and outputting a second one of the pair of amplified electric signals; wherein a source of each of the third and fourth P-type transistors is connected to a common voltage supply portion.

Claim 25

The amplifier circuit of claim 13, wherein, for each stage, the differential, common-source amplifier portion and the load portion have transistors having a first doping type, and the current mirror has transistors having a second doping type.

Claim 26

The amplifier circuit of claim 13, wherein, for each stage, the differential, common-source amplifier portion and the load portion each comprise PMOS transistors, and the current mirror comprises NMOS transistors.

Claim 27

The amplifier circuit of claim 13, wherein the pair of electric signals input to the first stage are generated by a transducer circuit and the pair of amplified electric signals output by the last stage are input to a sample and hold circuit.

Claim 28

The amplifier circuit of claim 23, wherein the transducer circuit comprises an electronic position encoder.

Claim 29

The amplifier circuit of claim 24, wherein the transducer circuit further comprises a multiplexer connected between the electronic position encoder and the differential common source amplifier portion of the first stage.

Claim 30

The amplifier circuit of claim 13, further comprising, for each stage: a first switch connected between a reference voltage and a first one of the pair of input signals; a second switch connected between the reference voltage and a second one of the pair of input signals; a third switch connected between a first one of the pair of amplified output signals and the first one of the pair of input signals; and a fourth switch connected between a second one of the pair of amplified output signals and the second one of the pair of input signals; wherein the first and second switches are commonly controlled and the third and fourth switches are commonly controlled.

Claim 31

The amplifier circuit of claim 26, further comprising, between each stage and an adjacent downstream stage, a pair of capacitors, each capacitor of the pair of capacitors connected in series with one output terminal of the stage and a corresponding input terminal of the adjacent downstream stage, each capacitor of the pair of capacitors connected upstream of a connection point of the corresponding one of the third and fourth switches.

Claim 32

The amplifier circuit of claim 13, wherein, in each stage: the differential common-source amplifier portion comprises input transistors having a doping type; and the load portion comprises a pair of diode-connected transistors that are the same doping type as the input transistors.