Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
207 words
A semiconductor memory device, comprising: a semiconductor substrate having a surface defining a plane extending substantially parallel to said surface; a multiplicity of memory cells disposed on said semiconductor substrate; each of said memory cells including a selection transistor having a gate terminal, a first electrode terminal and a second electrode terminal, said second electrode terminal having a contact metallizing layer with a given layer thickness; each of said memory cells including a storage capacitor being associated with and triggerable by said selection transistor, said storage capacitor having a ferroelectric dielectric, a first capacitor electrode and a second capacitor electrode, said storage capacitor being disposed in a trench formed inside said contact metallizing layer, said trench having a configuration projecting transversely to said plane resulting in said ferroelectric dielectric also projecting transversely to and upward from said plane, and said trench having a depth being equivalent to said given layer thickness; a word line to which said gate terminal of each of said selection transistors is connected; a bit line to which said first electrode terminal of each of said selection transistors is connected; and a common conductor layer of electrically conductive material to which said first capacitor electrode of each of said storage capacitors is connected.
Claim 2
Dependent Claim
207 words
A semiconductor memory device, comprising: a semiconductor substrate having a surface defining a plane extending substantially parallel to said surface; a multiplicity of memory cells disposed on said semiconductor substrate; each of said memory cells including a selection transistor having a gate terminal, a first electrode terminal and a second electrode terminal, said second electrode terminal having a contact metallizing layer with a given layer thickness; each of said memory cells including a storage capacitor being associated with and triggerable by said selection transistor, said storage capacitor having a ferroelectric dielectric, a first capacitor electrode and a second capacitor electrode, said storage capacitor being disposed in a trench formed inside said contact metallizing layer, said trench having a configuration projecting transversely to said plane resulting in said ferroelectric dielectric also projecting transversely to and upward from said plane, and said trench having a depth being equivalent to said given layer thickness; a word line to which said gate terminal of each of said selection transistors is connected; a bit line to which said first electrode terminal of each of said selection transistors is connected; and a common conductor layer of electrically conductive material to which said first capacitor electrode of each of said storage capacitors is connected.
Claim 3
Dependent Claim
35 words
The semiconductor memory device according to claim 1, wherein said configuration of said storage capacitor projecting upward from said plane is substantially cylinder-symmetrical and has a center cylinder axis extending approximately perpendicular to said plane.
Claim 4
Dependent Claim
34 words
The semiconductor memory device according to claim 1, wherein said trench has vertical side walls, and said second capacitor electrode inside said trench is a metal spacer deposited conformally onto said vertical side walls.
Claim 5
Dependent Claim
60 words
The semiconductor memory device according to claim 1, wherein said first capacitor electrode has an electrode segment being formed inside said trench and extending coaxially with a lengthwise extension of said trench and opposite said second capacitor electrode, and said ferroelectric dielectric is disposed at least between said electrode segment of said first capacitor electrode and said second capacitor electrode.
Claim 6
Dependent Claim
22 words
The semiconductor memory device according to claim 1, wherein said first capacitor electrode is U-shaped and disposed inside said second capacitor electrode.
Claim 7
Dependent Claim
31 words
The semiconductor memory device according to claim 1, wherein said trench is directly above said selection transistor, and including an insulating cover layer electrically insulating said trench from said selection transistor.