Method and apparatus for waking up a computer system via a parallel port

Claim 1

A method of powering up a computer system by a peripheral device connected to a parallel port of the computer system, the parallel port having a Select line, the method comprising: operating the computer system in a standby mode, whereby power consumption of the computer system is reduced; generating a signal at the peripheral device, the generating including: toggling the signal from a first level to a second level; and toggling back the signal from the second level to the first level; transmitting the signal to the Select line of the parallel port of the computer system; and in response to the receipt of the generated signal at the parallel port, powering up the computer system to a normal operating mode, wherein the powering up includes: detecting a transition in the level of the generated signal being toggled back from the second level to the first level.

Claim 2

A method of powering up a computer system by a peripheral device connected to a parallel port of the computer system, the parallel port having a Select line, the method comprising: operating the computer system in a standby mode, whereby power consumption of the computer system is reduced; generating a signal at the peripheral device, the generating including: toggling the signal from a first level to a second level; and toggling back the signal from the second level to the first level; transmitting the signal to the Select line of the parallel port of the computer system; and in response to the receipt of the generated signal at the parallel port, powering up the computer system to a normal operating mode, wherein the powering up includes: detecting a transition in the level of the generated signal being toggled back from the second level to the first level.

Claim 7

An apparatus for powering up a power supply of a computer system in response to a signal applied to a Select line of a parallel port of the computer system, the power supply being operable in a normal operating state and in a power save state in response to a signal applied to its control port, the apparatus comprising: a detection circuit coupled to the Select line of the parallel port, wherein the detection circuit generates a pulse in response to a signal on the Select line; and a circuit coupling the pulse to the control port of the power supply; wherein the signal applied to the Select line is toggled from a first level to a second level and then toggled back from the second level to the first level, wherein the detection circuit detects the transition in level of the signal on the Select line being toggled back from the second level to the first level.

Claim 8

An apparatus for powering up a power supply of a computer system in response to a signal applied to a Select line of a parallel port of the computer system, the power supply being operable in a normal operating state and in a power save state in response to a signal applied to its control port, the apparatus comprising: a detection circuit coupled to the Select line of the parallel port, wherein the detection circuit generates a pulse in response to a signal on the Select line; and a circuit coupling the pulse to the control port of the power supply; wherein the signal applied to the Select line is toggled from a first level to a second level and then toggled back from the second level to the first level, wherein the detection circuit detects the transition in level of the signal on the Select line being toggled back from the second level to the first level.

Claim 12

An apparatus for powering up a power supply of a computer system in response to a signal applied to a Select line of a parallel port of the computer system, wherein the signal toggles from a first level to a second level and toggles back from a second level to a first level, the power supply being operable in a normal operating state and in a power save state in response to a signal applied to its control port, the apparatus comprising: a detection circuit coupled to the Select line of the parallel port, wherein the detection circuit generates a pulse in response to the signal on the Select line; wherein the detection circuit detects the transition in level of the signal on the Select line being toggled back from a second level to a first level; a logic gate receiving the pulse from the detection circuit at a first input terminal, and receiving other pulses indicating a desired state of the computer system, and logically combining all the received pulses; an address detection circuit receiving a plurality of input signals and decoding them to provide an output signal; and a resettable latch having a clock terminal connected to receive the output signal from the address detection circuit, a reset terminal connected to receive an output signal from the logic gate, and a data terminal connected to receive a signal indicative of a desired power state of the computer system, wherein an output terminal of the latch is coupled to the control port of the power supply.

Claim 13

An apparatus for powering up a power supply of a computer system in response to a signal applied to a Select line of a parallel port of the computer system, wherein the signal toggles from a first level to a second level and toggles back from a second level to a first level, the power supply being operable in a normal operating state and in a power save state in response to a signal applied to its control port, the apparatus comprising: a detection circuit coupled to the Select line of the parallel port, wherein the detection circuit generates a pulse in response to the signal on the Select line; wherein the detection circuit detects the transition in level of the signal on the Select line being toggled back from a second level to a first level; a logic gate receiving the pulse from the detection circuit at a first input terminal, and receiving other pulses indicating a desired state of the computer system, and logically combining all the received pulses; an address detection circuit receiving a plurality of input signals and decoding them to provide an output signal; and a resettable latch having a clock terminal connected to receive the output signal from the address detection circuit, a reset terminal connected to receive an output signal from the logic gate, and a data terminal connected to receive a signal indicative of a desired power state of the computer system, wherein an output terminal of the latch is coupled to the control port of the power supply.