Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
268 words
An inter-hierarchy synchronizing system comprising: a higher-level functional hardware block for generating input event generation signals in accordance with a timing relation in a higher-level timing system in which timings are expressed by higher-level timing variables; a lower-level functional hardware block, arranged in a hierarchical structure in combination with said higher-level functional hardware block, for performing predetermined operations in accordance with a local timing relation in a local timing system in which timings are expressed by a local timing variable that is not necessarily coincident with said higher-level timing variables on the basis of activation signals, wherein requirements of said system are functionally decomposed into said lower-level and higher-level functional hardware blocks; and an inter-hierarchy synchronizing means, provided between said higher-level functional hardware block and said lower-level functional hardware block, for outputting said activation signals for activating said lower-level functional hardware block by said local timing system on the basis of said input event generation signals generated by said higher-level functional hardware block, supplying said activation signals to said lower-level functional hardware block, generating a task completion signal at said higher-level timing system when an output event generation signal generated from said lower-level functional hardware block is set to indicate that all tasks are completed by said lower-level functional hardware block, and supplying said task completion signal to said higher-level functional hardware block, wherein said system is arranged in a hierarchical structure in which said higher-level functional hardware block controls a plurality of lower-level functional hardware blocks each having a local timing system, and said inter-hierarchy synchronizing means activates said plurality of lower-level functional hardware blocks in parallel.
Claim 2
Dependent Claim
268 words
An inter-hierarchy synchronizing system comprising: a higher-level functional hardware block for generating input event generation signals in accordance with a timing relation in a higher-level timing system in which timings are expressed by higher-level timing variables; a lower-level functional hardware block, arranged in a hierarchical structure in combination with said higher-level functional hardware block, for performing predetermined operations in accordance with a local timing relation in a local timing system in which timings are expressed by a local timing variable that is not necessarily coincident with said higher-level timing variables on the basis of activation signals, wherein requirements of said system are functionally decomposed into said lower-level and higher-level functional hardware blocks; and an inter-hierarchy synchronizing means, provided between said higher-level functional hardware block and said lower-level functional hardware block, for outputting said activation signals for activating said lower-level functional hardware block by said local timing system on the basis of said input event generation signals generated by said higher-level functional hardware block, supplying said activation signals to said lower-level functional hardware block, generating a task completion signal at said higher-level timing system when an output event generation signal generated from said lower-level functional hardware block is set to indicate that all tasks are completed by said lower-level functional hardware block, and supplying said task completion signal to said higher-level functional hardware block, wherein said system is arranged in a hierarchical structure in which said higher-level functional hardware block controls a plurality of lower-level functional hardware blocks each having a local timing system, and said inter-hierarchy synchronizing means activates said plurality of lower-level functional hardware blocks in parallel.
Claim 3
Dependent Claim
50 words
The inter-hierarchy synchronizing system according to claim 1, wherein said inter-hierarchy synchronizing means includes a judging means for receiving task completion signals from said plurality of lower-level functional hardware blocks and generating said task completion signal when task completion signals from all of lower-level functional hardware blocks have been received.
Claim 4
Dependent Claim
97 words
The inter-hierarchy synchronizing system according to claim 2, wherein said inter-hierarchy synchronizing means assigns and sets estimation of timings which are determined according to a system requirement specification by said higher-level functional hardware block when the timings of signals defined in said lower-level functional hardware blocks and in said higher-level functional hardware block are used, and said lower-level functional hardware blocks report to said higher-level functional hardware block time interval variables expressed as a relationship between the estimation of timings and the timings defined in said lower-level functional hardware blocks and in said higher-level functional hardware block.
Claim 5
Dependent Claim
33 words
The inter-hierarchy synchronizing system according to claim 3, wherein a time interval variable is expressed as any one of a before-and-after relationship, a simultaneous relationship, a time in-and-out relationship and an unrelated relationship.
Claim 6
Dependent Claim
31 words
The inter-hierarchy synchronizing system according to claim 1, wherein at least any one of said higher-level functional hardware blocks and said lower-level functional hardware block has already been designed and library-registered.
Claim 7
Dependent Claim
57 words
The inter-hierarchy synchronizing system according to claim 1, wherein functions of said inter-hierarchy synchronizing means are realized by a timing simulation which is a simulation of timings with mutual relations and real timing simulation after an automatic logic synthesis by use of respective timing variables of said lower-level functional hardware block and said higher-level functional hardware block.