Method and system for synchronizing data having skew

Claim 2

A data transmission system having a plurality of transmitters, one or more receivers and a connection line connected between said transmitters and said receiver, wherein said transmitter includes transmission circuits for transmitting data in synchronism with a first clock, and said receiver includes reception circuits for receiving said transmitted data in synchronism with a second clock having a predetermined phase relationship with said first clock, a memory circuit for holding therein reception control information of said receiver associated with said respective transmitters, and a control circuit for controlling said reception circuits on the basis of said receiver control information, wherein said transmitter has an adjustment signal generation circuit for generating an adjustment signal, a data transmission circuit for outputting data to be transmitted, and a selector connected to said adjustment signal generation circuit and said data transmission circuit for selecting and outputting said adjustment signal and said data.

Claim 3

A data transmission system as set forth in claim 1, wherein said receiver has a latch array for adjusting a skew of said transmitted data and a data reception circuit connected to said latch array for receiving the data in synchronism with said second clock, and said control circuit controls said latch array on the basis of said receiver control information.

Claim 4

A data transmission system as set forth in claim 2, wherein said receiver has a reception phase judgement circuit for estimating an output of said latch array and for changing contents of said memory circuit on the basis of a judgement result of said reception phase judgement circuit.

Claim 5

A data transmission system as set forth in claim 3, wherein said reception phase judgement circuit includes a circuit for judging whether or not all bits of said adjustment signal can be synchronized with said second clock.

Claim 6

A data transmission system as set forth in claim 4, wherein said receiver has a data edge detection circuit for connecting an input and output of said latch array and judging whether or not said latch array can latch, said data edge detection circuit performs first condition setting of control to enable latching of bits of said adjustment signal, and said reception phase judgement circuit performs second condition setting of control to synchronize the bits of an all-data width of said adjustment signal with said second clock in same phase to change contents of said memory circuit on the basis of said first and second condition settings.

Claim 7

A data transmission system, comprising: a plurality of transmitters; one or more receivers; and a connection line connected between said transmitters and said receiver; wherein said transmitter includes transmission circuits for transmitting data in synchronism with a first clock; and said receiver includes reception circuits for receiving said transmitted data in synchronism with a second clock having a predetermined phase relationship with said first clock, a memory circuit for holding therein reception control information of said receiver associated with said respective transmitters, and a control circuit for controlling said reception circuits based on said receiver controller information, wherein said transmitter has an adjustment signal generation circuit for generating an adjustment signal, a data transmission circuit for outputting data to be transmitted, and a selector connected to said adjustment signal generation circuit and said data transmission circuit for selecting and outputting said adjustment signal and said data.

Claim 8

A data transmission system, comprising: a plurality of transmitters; one or more receivers; and a connection line connected between said transmitters and said receiver; wherein said transmitter includes transmission circuits for transmitting data in synchronism with a first clock; and said receiver includes reception circuits for receiving said transmitted data in synchronism with a second clock having a predetermined phase relationship with said first clock, a memory circuit for holding therein reception control information of said receiver associated with said respective transmitters, and a control circuit for controlling said reception circuits based on said receiver controller information, wherein said transmitter has an adjustment signal generation circuit for generating an adjustment signal, a data transmission circuit for outputting data to be transmitted, and a selector connected to said adjustment signal generation circuit and said data transmission circuit for selecting and outputting said adjustment signal and said data.

Claim 9

A data transmission system as set forth in claim 6, wherein said receiver includes a latch array for adjusting a skew of said transmitted data and a data reception circuit connected to said latch array for receiving the data in synchronism with said second clock, and said control circuit controls said latch array based on said receiver control information.

Claim 10

A data transmission system as set forth in claim 7, wherein said receiver includes a reception phase judgement circuit for estimating an output of said latch array and for changing contents of said memory circuit based on a judgement result of said reception phase judgement circuit.

Claim 11

A data transmission system as set forth in claim 8, wherein said reception phase judgement circuit includes a circuit for judging whether or not all bits of said adjustment signal can be synchronized with said second clock.

Claim 12

A data transmission system as set forth in claim 7, wherein said receiver includes a data edge detection circuit for connecting an input and output of said latch array and judging whether or not said latch array can latch, said data edge detection circuit performs first condition setting of control to enable latching of bits of said adjustment signal, and said reception phase judgement circuit performs second condition setting of control to synchronize the bits of an all-data with of said adjustment signal with said second clock in the same phase to change contents of said memory circuit based on said first and second condition settings.