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US5867423A
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US
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Memory circuit and method for multivalued logic storage by process variations
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1997-04-10
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Granted: 1999-02-02
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Expires: 2017-04-10
Abstract
Abstract A circuit and method which enables storage of more than two logic states in a memory cell by selectively setting threshold voltages of transistors in a memory array according to the present invention. In one embodiment, a memory circuit includes an array of storage transistors. Each storage transistor has a gate connected to an associated read line. When a read line is asserted, the current which flows through a selected storage transistor is indicative of the stored logic state. The current through each transistor is individually selected by setting the threshold voltage of each storage transistor during manufacture. Different transistors in the array are configured with differing threshold voltages to thereby represent different storage states. An analog-to-digital (A/D) converter is coupled to the selected storage transistor so as to sense the current and determine the state represented. Since each cell may represent one of more than two storage states, the memory circuit may advantageously allow an increased number of bits to be stored in each memory cell, thereby increasing the storage density and reducing the cost per bit.
Inventors
- 👤 Ashok Kapoor
- 👤 Alex Owens
- 👤 Thomas R. Wik
- 👤 Raymond T. Leung
- 👤 V. Swamy Irrinki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:09
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/5692; G11C7/00; G11C7/16
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
128 words
A memory circuit comprising: an array of transistors including at least a first transistor having a first threshold voltage and a second transistor having a second threshold voltage different from said first threshold voltage; an analog-to-digital converter coupled to detect a value indicative of a threshold voltage of a selected transistor within said array, wherein said analog-to-digital converter is configured to convert said value to one of at least three distinct digital values; an address decoder configured to assert a read signal in response to receiving an address signal, wherein assertion of said read signal results the detection of said value by said analog-to-digital converter; and a data gate configured to convert a multi-level logic signal from said analog-to-digital converter into binary data bits during a read operation.
Claim 2
Dependent Claim
128 words
A memory circuit comprising: an array of transistors including at least a first transistor having a first threshold voltage and a second transistor having a second threshold voltage different from said first threshold voltage; an analog-to-digital converter coupled to detect a value indicative of a threshold voltage of a selected transistor within said array, wherein said analog-to-digital converter is configured to convert said value to one of at least three distinct digital values; an address decoder configured to assert a read signal in response to receiving an address signal, wherein assertion of said read signal results the detection of said value by said analog-to-digital converter; and a data gate configured to convert a multi-level logic signal from said analog-to-digital converter into binary data bits during a read operation.
Claim 3
Dependent Claim
27 words
The memory circuit of claim 1, wherein said array further includes a third transistor having a third threshold voltage different from said first and second threshold voltages.
Claim 4
Dependent Claim
31 words
The memory circuit of claim 2, wherein said transistors each include a gate oxide, and wherein said threshold voltage difference is accomplished by causing the gate oxides to have differing thicknesses.
Claim 5
Dependent Claim
45 words
The memory circuit of claim 1, wherein said each transistor of said array includes a polysilicon gate, and wherein said threshold voltage difference is accomplished by doping the polysilicon with differing levels of an impurity which functions to alter a work function of the polysilicon.
Claim 6
Dependent Claim
35 words
The memory circuit of claim 1, wherein each transistor of said array includes a gate oxide, and wherein said threshold voltage difference is accomplished by causing the gate oxides to have differing excess charge densities.
Claim 7
Dependent Claim
29 words
The memory circuit of claim 1, wherein said analog-to-digital converter comprises a plurality of comparators, each coupled to compare said value to one of a plurality of reference voltages.
Claim 8
Dependent Claim
49 words
The memory circuit of claim 1, further comprising a sense amplifier coupled to detect a current through the selected transistor, wherein said current is indicative of the threshold voltage of the selected transistor, and wherein said sense amplifier is configured to responsively provide said value to said analog-to-digital converter.
Claim 9
Dependent Claim
226 words
A memory circuit comprising: an address decoder configured to assert a read signal in response to receiving an address signal; a data gate configured to convert m logic signals into n binary data bits during a read operation, wherein each of said logic signals has one of a number of distinct digital values, said number is at least three; an array of transistors including a first storage transistor having a first threshold voltage, and a second storage transistor having a second threshold voltage different from said first threshold voltage, wherein each of said storage transistors has a first terminal, a second terminal, and a gate, wherein said first terminal of the first storage transistor is coupled to a predetermined voltage, said gate of the first storage transistor is coupled to receive said read signal, and wherein said first storage transistor is configured to conduct a current indicative of the first threshold voltage when said read signal is asserted; a sense amplifier coupled to detect a voltage indicative of said current through said first storage transistor, said sense amplifier configured to responsively provide an input voltage; and an analog-to-digital converter coupled to detect said input voltage indicative of a voltage across said first storage transistor, wherein said analog to digital converter is configured to convert said input voltage to one of at least three distinct digital values.
Claim 10
Dependent Claim
226 words
A memory circuit comprising: an address decoder configured to assert a read signal in response to receiving an address signal; a data gate configured to convert m logic signals into n binary data bits during a read operation, wherein each of said logic signals has one of a number of distinct digital values, said number is at least three; an array of transistors including a first storage transistor having a first threshold voltage, and a second storage transistor having a second threshold voltage different from said first threshold voltage, wherein each of said storage transistors has a first terminal, a second terminal, and a gate, wherein said first terminal of the first storage transistor is coupled to a predetermined voltage, said gate of the first storage transistor is coupled to receive said read signal, and wherein said first storage transistor is configured to conduct a current indicative of the first threshold voltage when said read signal is asserted; a sense amplifier coupled to detect a voltage indicative of said current through said first storage transistor, said sense amplifier configured to responsively provide an input voltage; and an analog-to-digital converter coupled to detect said input voltage indicative of a voltage across said first storage transistor, wherein said analog to digital converter is configured to convert said input voltage to one of at least three distinct digital values.
Claim 11
Dependent Claim
60 words
The memory circuit of claim 8, wherein said analog-to-digital converter comprises a number of comparators, each coupled to compare said input voltage to one of a number of reference voltages, wherein said number of comparators equals said number of reference voltages, and wherein said number of reference voltages is equal to one less than said number of distinct digital values.
Claim 12
Independent Claim
202 words
A method for storing more than two logic states in a memory cell, comprising the steps of: fabricating an array of storage transistors wherein each storage transistor has a threshold voltage, a first terminal, a second terminal, and a gate, wherein said first terminal is coupled to a predetermined voltage, wherein said second terminal is coupled to one of a plurality of read data lines, wherein said gate is coupled to receive one of a plurality of read signals, wherein each storage transistor is configured to conduct a current indicative of the threshold voltage when a corresponding read signal is asserted, wherein said array includes a first storage transistor having a first threshold voltage, and a second storage transistor having a second threshold voltage, said first threshold voltage differs from said second threshold voltage; fabricating an analog-to-digital converter coupled to detect a value indicative of a voltage across one of said storage transistors, wherein said analog to digital converter is configured to convert said value to one of at least three distinct digital values; and fabricating a data gate configured to convert m logic signals, each having one of said distinct digital values, into n binary data bits during a read operation.
Claim 13
Independent Claim
202 words
A method for storing more than two logic states in a memory cell, comprising the steps of: fabricating an array of storage transistors wherein each storage transistor has a threshold voltage, a first terminal, a second terminal, and a gate, wherein said first terminal is coupled to a predetermined voltage, wherein said second terminal is coupled to one of a plurality of read data lines, wherein said gate is coupled to receive one of a plurality of read signals, wherein each storage transistor is configured to conduct a current indicative of the threshold voltage when a corresponding read signal is asserted, wherein said array includes a first storage transistor having a first threshold voltage, and a second storage transistor having a second threshold voltage, said first threshold voltage differs from said second threshold voltage; fabricating an analog-to-digital converter coupled to detect a value indicative of a voltage across one of said storage transistors, wherein said analog to digital converter is configured to convert said value to one of at least three distinct digital values; and fabricating a data gate configured to convert m logic signals, each having one of said distinct digital values, into n binary data bits during a read operation.
Claim 14
Dependent Claim
39 words
The method of claim 10, further comprising the steps of: adjusting a first set of said storage transistors to have a first threshold voltage; and adjusting a second set of said storage transistors to have a second threshold voltage.
Claim 15
Dependent Claim
39 words
The method of claim 11, wherein said storage transistors have gates comprised of polysilicon, and wherein one of said adjustments is accomplished by doping the polysilicon with an impurity so as to alter the work function of the gates.
Claim 16
Dependent Claim
32 words
The method of claim 11, wherein said storage transistors include a gate oxide having interface states, and wherein one of said adjustments is accomplished by altering the density of said interface states.
Claim 17
Dependent Claim
28 words
The method of claim 11, wherein said storage transistors include a gate oxide having a thickness, and wherein one of said adjustments is accomplished by altering the thickness.
Claim 18
Dependent Claim
34 words
The method of claim 11, further comprising the step of fabricating an address decoder configured to assert said one of said read signals in response to receiving an address signal and an enable signal.
Claim 19
Dependent Claim
37 words
The method of claim 11, further comprising the step of fabricating a sense amplifier coupled to detect said current, said sense amplifier configured to responsively provide said value to said analog-to-digital converter. Please add the following claims.
Claim 20
Dependent Claim
129 words
A memory circuit comprising: an array of transistors including at least a first transistor having a first threshold voltage and a second transistor having a second threshold voltage different from said first threshold voltage; an analog-to-digital converter coupled to detect a value indicative of a threshold voltage of a selected transistor within said array, wherein said analog-to-digital converter is configured to convert said value to one of at least three distinct digital values; and an address decoder configured to assert a read signal in response to receiving an address signal, wherein assertion of said read signal results the detection of said value by said analog-to-digital converter; wherein said analog-to-digital converter comprises a plurality of comparators, each coupled to compare said value to one of a plurality of reference voltages.
Claim 21
Dependent Claim
129 words
A memory circuit comprising: an array of transistors including at least a first transistor having a first threshold voltage and a second transistor having a second threshold voltage different from said first threshold voltage; an analog-to-digital converter coupled to detect a value indicative of a threshold voltage of a selected transistor within said array, wherein said analog-to-digital converter is configured to convert said value to one of at least three distinct digital values; and an address decoder configured to assert a read signal in response to receiving an address signal, wherein assertion of said read signal results the detection of said value by said analog-to-digital converter; wherein said analog-to-digital converter comprises a plurality of comparators, each coupled to compare said value to one of a plurality of reference voltages.
Claim 22
Dependent Claim
27 words
The memory circuit of claim 17, wherein said array further includes a third transistor having a third threshold voltage different from said first and second threshold voltages.
Claim 23
Dependent Claim
45 words
The memory circuit of claim 17, wherein said each transistor of said array includes a polysilicon gate, and wherein said threshold voltage difference is accomplished by doping the polysilicon with differing levels of an impurity which functions to alter a work function of the polysilicon.
Claim 24
Dependent Claim
35 words
The memory circuit of claim 17, wherein each transistor of said array includes a gate oxide, and wherein said threshold voltage difference is accomplished by causing the gate oxides to have differing excess charge densities.
Claim 25
Dependent Claim
31 words
The memory circuit of claim 18, wherein said transistors each include a gate oxide, and wherein said threshold voltage difference is accomplished by causing the gate oxides to have differing thicknesses.
Claim 26
Dependent Claim
49 words
The memory circuit of claim 17, further comprising a sense amplifier coupled to detect a current through the selected transistor, wherein said current is indicative of the threshold voltage of the selected transistor, and wherein said sense amplifier is configured to responsively provide said value to said analog-to-digital converter.
References Cited (Backward Citations)
US4057788A
Cited
US4661929A
Cited
US5119330A
Cited
US5172338A
Cited
US5172338B1
Cited
US5394362A
Cited
US5521865A
Cited
US5508958A
Cited
US5638320A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-01 | 2002-08-03 | 2003-02-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-01 | 2006-08-03 | 2007-02-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-01 | 2010-08-03 | 2011-02-02 | $7700.00 | Window Closed / Lapsed |