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US5867012A Expired / Lapsed US ⏱️ 0.0 years remaining

Switching bandgap reference circuit with compounded ΔV.sub.βΕ

Assignee: Analog Devices Inc
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Filing: 1997-08-14
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Granted: 1999-02-02
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Expires: 2017-08-14
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Abstract

Abstract A switching bandgap reference circuit with compounded ΔV BE includes an amplifier having an output, an inverting input and a non-inverting input; a first PN junction connected to the non-inverting input; a second PN junction connected to the inverting input through an input capacitor; a low current source and a high current source; a switching device for applying in the auto zero mode the low current source to a first terminal of the first PN junction and the high current source to a first terminal of the second PN junction for establishing the V BE , of the first junction at both the inputs of the amplifier and for applying in the valid reference mode the high current source to the first terminal of the first PN junction and the low current source to the first terminal of the second PN junction for establishing the positive ΔV BE , of the first PN junction to both the inputs of the amplifier and applying the negative ΔV BE2 of the second PN junction to the input capacitor to produce a voltage of ΔV BE1 plus (-ΔV BE2 ) across the input capacitor; a feedback capacitor connected between the output and inverting input of the amplifier to define the gain on the combined ΔV BE voltages to produce a temperature stabilized voltage at the output of the amplifier and a reset switching device for discharging the feedback capacitor and enabling the amplifier to equalize its inputs in the auto zero mode.

Inventors

  • 👤 Michael G. Tuthill

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 20:46
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/30

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 248 words
A switching bandgap reference circuit with compounded ΔV BE , comprising: an amplifier having an output, an inverting input and a non-inverting input; a first PN junction connected to said non-inverting input; a second PN junction connected to said inverting input through an input capacitor; a low current source and a high current source; a switching device for applying in an auto zero mode the low current source to a first terminal of said first PN junction and the high current source to a first terminal of said second PN junction for establishing a V BE1 of said first PN junction at both said inputs of said amplifier, and for applying in a valid reference mode the high current source to said first terminal of said first PN junction and the low current source to said first terminal of said second PN junction for establishing a positive ΔV BE1 of said first PN junction to both said inputs of said amplifier and applying a negative ΔV BE2 of said second PN junction to said input capacitor to produce a voltage of ΔV BE1 plus (-ΔV BE2 ) across said input capacitor; a feedback capacitor connected between the output and inverting input of said amplifier to define the gain on a combined ΔV BE voltage to produce a temperature stabilized voltage at the output of said amplifier; and a reset switching device for discharging said feedback capacitor and enabling said amplifier to equalize its inputs in the auto-zero mode.
Claim 2
Dependent Claim 248 words
A switching bandgap reference circuit with compounded ΔV BE , comprising: an amplifier having an output, an inverting input and a non-inverting input; a first PN junction connected to said non-inverting input; a second PN junction connected to said inverting input through an input capacitor; a low current source and a high current source; a switching device for applying in an auto zero mode the low current source to a first terminal of said first PN junction and the high current source to a first terminal of said second PN junction for establishing a V BE1 of said first PN junction at both said inputs of said amplifier, and for applying in a valid reference mode the high current source to said first terminal of said first PN junction and the low current source to said first terminal of said second PN junction for establishing a positive ΔV BE1 of said first PN junction to both said inputs of said amplifier and applying a negative ΔV BE2 of said second PN junction to said input capacitor to produce a voltage of ΔV BE1 plus (-ΔV BE2 ) across said input capacitor; a feedback capacitor connected between the output and inverting input of said amplifier to define the gain on a combined ΔV BE voltage to produce a temperature stabilized voltage at the output of said amplifier; and a reset switching device for discharging said feedback capacitor and enabling said amplifier to equalize its inputs in the auto-zero mode.
Claim 3
Dependent Claim 16 words
The switching bandgap reference circuit of claim 1 in which said amplifier is an operational amplifier.
Claim 4
Dependent Claim 25 words
The switching bandgap reference circuit of claim 1 in which at least one of said first or second PN junctions is included in a diode.
Claim 5
Dependent Claim 25 words
The switching bandgap reference circuit of claim 1 in which at least one of said first or second PN junctions is included in a transistor.
Claim 6
Dependent Claim 26 words
The switching bandgap reference circuit of claim 1 in which at least one of said first or second PN junctions is included in a bipolar transistor.
Claim 7
Dependent Claim 32 words
The switching bandgap reference circuit of claim 1 in which at least one of said first or second PN junctions is included in a parasitic substrate bipolar transistor in a CMOS circuit.
Claim 8
Dependent Claim 18 words
The switching bandgap reference circuit of claim 6 in which said transistors include a collector connected to ground.
Claim 9
Dependent Claim 33 words
The switching bandgap reference circuit of claim 1 in which said first PN junction has a second terminal connected to a common node to establish the amplifier output voltage relative to that node.
Claim 10
Dependent Claim 15 words
The switching bandgap reference circuit of claim 8 in which said common node is ground.

References Cited (Backward Citations)

US5352972A Cited
US5563504A Cited
US5686823A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-02-01 2002-08-03 2003-02-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-02-01 2006-08-03 2007-02-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-02-01 2010-08-03 2011-02-02 $7700.00 Window Closed / Lapsed

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