US5864688A
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US
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Apparatus and method for positively and subtractively decoding addresses on a bus
Assignee: Hewlett Packard Development Co LP
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Filing: 1996-07-19
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Granted: 1999-01-26
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Expires: 2016-07-19
Abstract
Abstract A computer system having an expansion base for docking a portable portion of the computer system includes a bridge circuit for adaptively decoding addresses on a bus based on the docking status. Both the expansion base and the portable portion include the bridge circuit for passing cycles from a peripheral component interconnect (PCI) bus to an industry standard architecture (ISA) bus. The bridge includes internal devices and configuration registers for controlling the decoding. Bus cycles intended for internal devices and external devices connected to each respective ISA bus of the bridge circuits are positively decoded. Cycles not positively decoded and claimed are subtractively decoded by one of the bridge circuits depending on the docking status.
Inventors
- 👤 Gregory N. Santos
- 👤 David J. Maguire
- 👤 Dwight D. Riley
- 👤 James R. Edwards
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 06:46
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F13/4045
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
203 words
A computer system, comprising: a processor for providing bus cycles; a mezzanine bus coupled to said processor for carrying the bus cycles; a first input/output bus; a first bridge coupled between said mezzanine bus and said first input/output bus, said first bridge having a first address decoder which positively decodes and claims a bus cycle intended for said first input/output bus, said first address decoder further including the capability to selectively subtractively decode and claim a bus cycle; a second input/output bus; and a second bridge coupled between said mezzanine bus and said second input/output bus, said second bridge having a second address decoder which positively decodes and claims a bus cycle intended for said second input/output bus, said second address decoder further including the capability to selectively subtractively decode and claim a bus cycle, wherein said first bridge subtractively decodes and claims bus cycles if said first bridge subtractive decoding is enabled and said second bridge subtractive decoding is disabled, and wherein said first bridge does not claim bus cycles not positively decoded and said second bridge subtractively decodes and claims bus cycles not positively decoded if said second bridge subtractive decoding is enabled and said first bridge subtractive decoding is disabled.
Claim 2
Dependent Claim
117 words
The computer system of claim 1, wherein said mezzanine bus is comprised of a first portion and a second portion, said first and second portions being connectable by a connector, said first portion being coupled to said processor, and wherein said first bridge is coupled to said first portion and said second bridge is coupled to said second portion, said computer system further comprising: means for detecting when said first and second portions are connected, wherein if said first and second portions are unconnected, said first bridge subtractively decodes and claims bus cycles, and wherein if said first and second portions are connected, only one of said first and second bridges subtractively decodes and claims bus cycles.
Claim 3
Dependent Claim
75 words
The computer system of claim 2, further comprising: a first input/output device coupled to said first input/output bus, said first input/output device being addressable at a first address range; and a second input/output device coupled to said second input/output bus, said second input/output device being addressable at a second address range, wherein said first and second bridges each include configuration registers for selectively enabling the decoding of addresses to said first and second address ranges.
Claim 4
Dependent Claim
20 words
The computer system of claim 3, wherein said first and second input/output devices are identical at an identical address range.
Claim 5
Dependent Claim
75 words
The computer system of claim 1, further comprising: a first input/output device coupled to said first input/output bus, said first input/output device being addressable at a first address range; and a second input/output device coupled to said second input/output bus, said second input/output device being addressable at a second address range, wherein said first and second bridges each include configuration registers for selectively enabling the decoding of addresses to said first and second address ranges.
Claim 6
Dependent Claim
20 words
The computer system of claim 5, wherein said first and second input/output devices are identical at an identical address range.
Claim 7
Dependent Claim
55 words
The computer system of claim 1, wherein said first and second bridges contain a configuration bit for enabling subtractive decoding, said first and second address decoders subtractively decoding addresses when said bit indicates subtractive decoding is enabled, said first and second address decoders only positively decoding addresses when said bit indicates subtractive decoding is disabled.
Claim 8
Dependent Claim
17 words
The computer system of claim 1, wherein said mezzanine bus is a peripheral component interconnect (PCI) bus.
Claim 9
Dependent Claim
19 words
The computer system of claim 1, wherein said first and second input/output buses are industry standard architecture (ISA) buses.
Claim 10
Dependent Claim
228 words
A computer system, comprising: an input device for receiving input from a user; a processor for providing bus cycles to said input device; a mezzanine bus coupled to said processor for carrying the bus cycles; a first input/output bus; a first bridge coupled between said mezzanine bus and said first input/output bus, said first bridge having a first address decoder which positively decodes and claims a bus cycle intended for said first input/output bus, said first address decoder further including the capability to selectively subtractively decode and claim a bus cycle; a second input/output bus; and a second bridge coupled between said mezzanine bus and said second input/output bus, said second bridge having a second address decoder which positively decodes and claims a bus cycle intended for said second input/output bus, said second address decoder further including the capability to selectively subtractively decode and claim a bus cycle, wherein said input device is attachable to said first and second buses, wherein said first bridge subtractively decodes and claims bus cycles if said first bridge subtractive decoding is enabled and said second bridge subtractive decoding is disabled, and wherein said first bridge does not claim bus cycles not positively decoded and said second bridge subtractively decodes and claims bus cycles not positively decoded if said second bridge subtractive decoding is enabled and said first bridge subtractive decoding is disabled.
Claim 11
Dependent Claim
109 words
The computer system of claim 10, wherein said mezzanine bus is comprised of a first portion and a second portion, said first and second portions being connectable by a connector, and wherein said first bridge is coupled to said first portion and said second bridge is coupled to said second portion, said computer system further comprising: means for detecting when said first and second portions are connected; wherein if said first and second portions are unconnected, said first bridge subtractively decodes and claims bus cycles, and wherein if said first and second portions are connected, only one of said first and second bridges subtractively decodes and claims bus cycles.
Claim 12
Dependent Claim
75 words
The computer system of claim 11, further comprising: a first input/output device coupled to said first input/output bus, said first input/output device being addressable at a first address range; and a second input/output device coupled to said second input/output bus, said second input/output device being addressable at a second address range, wherein said first and second bridges each include configuration registers for selectively enabling the decoding of addresses to said first and second address ranges.
Claim 13
Dependent Claim
20 words
The computer system of claim 12, wherein said first and second input/output devices are identical at an identical address range.
Claim 14
Dependent Claim
75 words
The computer system of claim 10, further comprising: a first input/output device coupled to said first input/output bus, said first input/output device being addressable at a first address range; and a second input/output device coupled to said second input/output bus, said second input/output device being addressable at a second address range, wherein said first and second bridges each include configuration registers for selectively enabling the decoding of addresses to said first and second address ranges.
Claim 15
Dependent Claim
20 words
The computer system of claim 14, wherein said first and second input/output devices are identical at an identical address range.
Claim 16
Dependent Claim
55 words
The computer system of claim 10, wherein said first and second bridges contain a configuration bit for enabling subtractive decoding, said first and second address decoders subtractively decoding addresses when said bit indicates subtractive decoding is enabled, said first and second address decoders only positively decoding addresses when said bit indicates subtractive decoding is disabled.
Claim 17
Dependent Claim
17 words
The computer system of claim 10, wherein said mezzanine bus is a peripheral component interconnect (PCI) bus.
Claim 18
Dependent Claim
19 words
The computer system of claim 10, wherein said first and second input/output buses are industry standard architecture (ISA) buses.
Claim 19
Dependent Claim
17 words
The computer system of claim 10, further including: a mass storage system; and a video display system.
Claim 20
Dependent Claim
210 words
A computer system, comprising: a mobile portion including: a processor for providing bus cycles; a mezzanine bus coupled to said processor; a first input/output bus; and a first bridge coupled between said mezzanine bus and said first input/output bus, said first bridge having a first address decoder which positively decodes and claims a bus cycle intended for said first input/output bus, said first address decoder further including the capability to selectively subtractively decode and claim a bus cycle; and an expansion base portion connectable to said mobile portion, including: a mezzanine extension bus connected to said mezzanine bus when said mobile portion is connected to said expansion base portion; a second input/output bus; and a second bridge coupled between said mezzanine expansion bus and said second input/output bus, said second bridge having a second address decoder which positively decodes and claims a bus cycle intended for said second input/output bus, said second address decoder further including the capability to selectively subtractively decode and claim a bus cycle, wherein said first bridge does not claim bus cycles not positively decoded and said second bridge subtractively decodes and claims bus cycles, and wherein if said mobile portion is unconnected to said expansion base, said first bridge subtractively decodes and claims bus cycles.
Claim 21
Dependent Claim
59 words
The computer system of claim 20, wherein if said mobile portion is connected to said expansion base, said first bridge does not claim bus cycles not positively decoded and said second bridge subtractively decodes and claims bus cycles, and wherein if said mobile portion is unconnected to said expansion base, said first bridge subtractively decodes and claims bus cycles.
Claim 22
Dependent Claim
17 words
The computer system of claim 20, wherein said mezzanine bus is a peripheral component interconnect (PCI) bus.
Claim 23
Dependent Claim
19 words
The computer system of claim 20, wherein said first and second input/output buses are industry standard architecture (ISA) buses.
Claim 24
Independent Claim
226 words
A method of decoding addresses in a computer system, the computer system including a processor for providing bus cycles; a mezzanine bus coupled to said processor for carrying the bus cycles; a first input/output bus; a first bridge coupled between said mezzanine bus and said first input/output bus, said first bridge having a first address decoder which positively decodes and claims a bus cycle intended for said first input/output bus, said first address decoder further including the capability to selectively subtractively decode and claim a bus cycle; a second input/output bus; and a second bridge coupled between said mezzanine bus and said second input/output bus, said second bridge having a second address decoder which positively decodes and claims a bus cycle intended for said second input/output bus, said second address decoder further including the capability to selectively subtractively decode and claim a bus cycle, the method comprising the steps of: configuring said first bridge to perform positive decoding only; configuring said second bridge to perform positive and subtractive decoding; said processor providing a bus cycle to a device; said first bridge decoding and claiming said bus cycle only if said device is coupled to said first bus; and said second bridge decoding and claiming said bus cycle if said device is coupled to said second bridge or said first bridge does not claim the bus cycle.
Claim 25
Dependent Claim
41 words
The method of claim 24, further comprising the steps of: configuring said first bridge to perform positive and subtractive decoding; disabling said second bridge; providing a bus cycle to a device; and said first bridge decoding and claiming said bus cycle.
Claim 26
Dependent Claim
16 words
The method of claim 24, wherein said mezzanine bus is a peripheral component interconnect (PCI) bus.
Claim 27
Dependent Claim
18 words
The method of claim 24, wherein said first and second input/output buses are industry standard architecture (ISA) buses.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-25 | 2002-07-27 | 2003-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-25 | 2006-07-27 | 2007-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-25 | 2010-07-27 | 2011-01-26 | $7700.00 | Window Closed / Lapsed |