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Patent US5864548A successfully refreshed from Google Patents.
US5864548A
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Method and apparatus for fast modulation in synchronous CDMA communications
Assignee: BEIJING XINWEI TELECOM TECHNOLOGY Co Ltd
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Filing: 1997-01-06
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Granted: 1999-01-26
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Expires: 2017-01-06
Abstract
Abstract A system and method for modulating synchronous CDMA (S-CDMA) signals in antenna array wireless system. By taking advantage of the symmetric property of Walsh code words utilized in S-CDMA perform modulation of signals intended for a plurality of users. The system includes a Fast Hadamard Transform (FHT) Processor that realizes baseband operations including spreading and digital combining in one step. In addition to significant reduction in computations and storage over prior methods, the invention also provides substantial advantages in hardware implementation. While the exemplary embodiment is described in the context of antenna array CDMA systems, the disclosed techniques have general applications in CDMA systems with arbitrary symbol values.
Inventors
- 👤 Hui Liu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 12:21
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/69; H04B1/707
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
206 words
A synchronous code-division multiple access (S-CDMA) modulator for modulating P signals with a plurality L of Walsh orthogonal codes of order L to generate L output chip signals within a symbol period in synchronous CDMA communications, the modulator comprising: a Fast Hadamard Transform (FHT) Processor including a plurality L inputs for receiving L input signals, wherein the L input signals include the P signals, wherein the FHT processor includes one or more outputs for generating L output chip signals, wherein the FHT processor performs a Fast Hadamard Transform on the L input signals to produce the L output chip signals, wherein the FHT processor is operable to perform spreading and combining on said L input signals to produce said L output chip signals; an input buffer coupled to said plurality L inputs of said FHT processor, wherein said input buffer comprises L elements for storing said P signals, wherein said input buffer is operable to apply said P signals to the plurality L inputs of said Fast Hadamard Transform Processor; wherein L is a power-of-2 integer and P is a positive integer less than or equal to L; wherein said one or more output chip signals are transmittable in a predetermined order to accomplish S-CDMA communications.
Claim 2
Dependent Claim
206 words
A synchronous code-division multiple access (S-CDMA) modulator for modulating P signals with a plurality L of Walsh orthogonal codes of order L to generate L output chip signals within a symbol period in synchronous CDMA communications, the modulator comprising: a Fast Hadamard Transform (FHT) Processor including a plurality L inputs for receiving L input signals, wherein the L input signals include the P signals, wherein the FHT processor includes one or more outputs for generating L output chip signals, wherein the FHT processor performs a Fast Hadamard Transform on the L input signals to produce the L output chip signals, wherein the FHT processor is operable to perform spreading and combining on said L input signals to produce said L output chip signals; an input buffer coupled to said plurality L inputs of said FHT processor, wherein said input buffer comprises L elements for storing said P signals, wherein said input buffer is operable to apply said P signals to the plurality L inputs of said Fast Hadamard Transform Processor; wherein L is a power-of-2 integer and P is a positive integer less than or equal to L; wherein said one or more output chip signals are transmittable in a predetermined order to accomplish S-CDMA communications.
Claim 3
Dependent Claim
69 words
The S-CDMA modulator as defined by claim 1, wherein said input buffer comprises L elements for storing said P signals and also for storing L-P zeros; wherein said input buffer is operable to apply said P signals and said L-P zeros to the plurality L inputs of said Fast Hadamard Transform Processor wherein the L input signals to the FHT Processor include the P signals and said L-P zeros.
Claim 4
Dependent Claim
127 words
The S-CDMA modulator as defined by claim 2, wherein said input buffer stores said L inputs for application to said Fast Hadamard Transform Processor; wherein each of said L inputs of said FHT processor corresponds to one of said plurality L Walsh orthogonal codes; wherein said input buffer is operable to store each of said P signals at a position corresponding to a respective input of said FHT processor, wherein, for each respective signal of said P signals, the respective input of said FHT processor corresponds to the orthogonal Walsh code used to spread the respective signal; wherein said input buffer is operable to store zeros in any remaining wherein said input buffer is operable to store zeros in any remaining L-P elements of said input buffer.
Claim 5
Dependent Claim
54 words
The S-CDMA modulator as defined by claim 1, further comprising: an output buffer coupled to said one or more outputs of said FHT processor for storing said L output chip signals of said Fast Hadamard Transform Processor, wherein said output buffer is operable to output said L output chip signals in a pre-determined order.
Claim 6
Dependent Claim
156 words
The S-CDMA modulator as defined by claim 1, wherein said modulator is operable for use in an antenna array system, wherein the antenna array comprises M antennas; the modulator further comprising: a plurality P multipliers each having first and second inputs and an output, wherein said first input of each of said P multipliers is coupled to receive a respective symbol, wherein said second input of each of said P multipliers is coupled to receive a respective beamforming coefficient, wherein each of said plurality P multipliers is operable to multiply said respective P symbol with said respective beamforming coefficient to produce said P signals at said output, wherein said outputs of each of said plurality P multipliers are coupled to said FHT processor to provide said P signals to said FHT processor; wherein the S-CDMA modulator is operable to perform spreading, beamforming and combining on said L input signals to produce said L output chip signals.
Claim 7
Independent Claim
119 words
A method for performing synchronous code-division multiple access (S-CDMA) modulation for modulating P signals with a plurality L of Walsh orthogonal codes of order L to generate L output chip signals within a symbol period in synchronous CDMA communications, the method comprising: receiving L input signals, wherein the L input signals include the P signals; performing a Fast Hadamard Transform on the L input signals to produce the L output chip signals, wherein said performing the Fast Hadamard Transform performs spreading and combining on said L input signals to produce said L output chip signals; generating said L output chip signals; wherein L is a power-of-2 integer and P is a positive integer less than or equal to L.
Claim 8
Independent Claim
119 words
A method for performing synchronous code-division multiple access (S-CDMA) modulation for modulating P signals with a plurality L of Walsh orthogonal codes of order L to generate L output chip signals within a symbol period in synchronous CDMA communications, the method comprising: receiving L input signals, wherein the L input signals include the P signals; performing a Fast Hadamard Transform on the L input signals to produce the L output chip signals, wherein said performing the Fast Hadamard Transform performs spreading and combining on said L input signals to produce said L output chip signals; generating said L output chip signals; wherein L is a power-of-2 integer and P is a positive integer less than or equal to L.
Claim 9
Dependent Claim
21 words
The method of claim 6, further comprising: transmitting said L output chip signals in a pre-determined order to accomplish S-CDMA communications.
Claim 10
Dependent Claim
17 words
The method of claim 6, wherein the L input signals include the P signals and L-P zeros.
Claim 11
Dependent Claim
91 words
The method of claim 8, further comprising: storing said P signals and said L-P zeros in an input buffer, wherein said input buffer comprises L elements; and applying said P signals and said L-P zeros from said input buffer to a plurality L inputs of a Fast Hadamard Transform (FHT)processor; wherein said receiving L input signals is performed in response to said applying; wherein said performing a Fast Hadamard Transform comprises the FHT processor performing a Fast Hadamard Transform on the L input signals to produce the L output chip signals.
Claim 12
Dependent Claim
103 words
The method of claim 9, further comprising: wherein each of said L inputs of said FHT processor corresponds to one of said plurality L Walsh orthogonal codes; wherein said storing said P signals and said L-P zeros in an input buffer comprises storing each of said P signals at a position corresponding to a respective input of said FHT processor, wherein, for each respective signal of said P signals, the respective input of said FHT processor corresponds to the orthogonal Walsh code used to spread the respective signal; wherein said storing includes storing zeros in any remaining L-P elements of said input buffer.
Claim 13
Dependent Claim
28 words
The method of claim 6, storing said L output chip signals of said Fast Hadamard Transform Processor; and outputting said L output chip signals in a pre-determined order.
Claim 14
Dependent Claim
60 words
The method of claim 6, further comprising: multiplying a respective P symbol with a respective beamforming coefficient to produce said P signals, wherein said multiplying is performed prior to said receiving said L input signals; wherein the S-CDMA modulation method is operable to perform spreading, beamforming and combining on said L input signals to produce said L output chip signals.
References Cited (Backward Citations)
US5463657A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-25 | 2002-07-27 | 2003-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-25 | 2006-07-27 | 2007-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-25 | 2010-07-27 | 2011-01-26 | $7700.00 | Window Closed / Lapsed |