Process for manufacturing a multi layer bumped semiconductor device

Claim 1

A method for fabricating a chip size package (32) comprising the steps of: forming a laminated substrate (10) consisting of a dielectric layer (12) and a high conductive layer (14) disposed thereon; drilling holes (16) into the dielectric layer (12) to expose selective solderable areas on a bottom side of said conductive layer (12); applying a desired pattern to the conductive layer (14); forming a chip structure (18) consisting of a silicon die (20) having bonding pads (23); forming an insulating layer (22) disposed on the top surface of said silicon die (20), said insulating layer (22) being formed to expose the bonding pads (23) on the top surface of said silicon die (20); applying gold bumps (24) to the bonding pads (23) on the top surface of the silicon die (20); bonding the laminated substrate (10) to the chip structure (18) via the holes (16) exposing the selective solderable areas on the bottom side of the conductive layer (12) and using the gold bumps (24) on the top surface of the bonding pads (23) of the silicon die (20) to connect to said selective solderable areas on the bottom side of said conductive layer through said drilled holes in the dielectric layer of said laminated substrate; applying a solder mask (26) over the top surface of the conductive layer (14) of the laminated substrate so as to form selective solder areas (28) in the top surface of the conductive layer (14) of the laminated substrate (10); attaching solder balls (30) to the selective solder areas (28); and thereby providing a fabricated chip size package (32).

Claim 2

A method for fabricating a chip size package (32) comprising the steps of: forming a laminated substrate (10) consisting of a dielectric layer (12) and a high conductive layer (14) disposed thereon; drilling holes (16) into the dielectric layer (12) to expose selective solderable areas on a bottom side of said conductive layer (12); applying a desired pattern to the conductive layer (14); forming a chip structure (18) consisting of a silicon die (20) having bonding pads (23); forming an insulating layer (22) disposed on the top surface of said silicon die (20), said insulating layer (22) being formed to expose the bonding pads (23) on the top surface of said silicon die (20); applying gold bumps (24) to the bonding pads (23) on the top surface of the silicon die (20); bonding the laminated substrate (10) to the chip structure (18) via the holes (16) exposing the selective solderable areas on the bottom side of the conductive layer (12) and using the gold bumps (24) on the top surface of the bonding pads (23) of the silicon die (20) to connect to said selective solderable areas on the bottom side of said conductive layer through said drilled holes in the dielectric layer of said laminated substrate; applying a solder mask (26) over the top surface of the conductive layer (14) of the laminated substrate so as to form selective solder areas (28) in the top surface of the conductive layer (14) of the laminated substrate (10); attaching solder balls (30) to the selective solder areas (28); and thereby providing a fabricated chip size package (32).