Apparatus and methods for routing data packets through a processing system network

Claim 3

The apparatus as set forth in claim 1 wherein first sub-network and said second sub-network is one of a local area network and a wide area said control circuit is operative to determine whether both a first sub-network and a second sub-network are local area networks.

Claim 4

The apparatus as set forth in claim 2 wherein said control circuit, in the event that both said first sub-network and said second sub-network are local area networks, is further operative to store a routing address retrieved from said first means in said second means.

Claim 5

The apparatus as set forth in claim 1 wherein said control circuit, in the event that a routing address is not stored in said second means, is operative to determine whether a received data packet requires special processing.

Claim 6

The apparatus as set forth in claim 4 wherein said control circuit, in the event that said received data packet does not require special processing, is further operative to store said routing address in said second means.

Claim 7

The apparatus as set forth in claim 1 wherein said control circuit is operative to access initially said second means and, in the event that said routing address data is not stored in said second means, to access said first means.

Claim 8

The apparatus as set forth in claim 1 wherein said control circuit is operative to access initially substantially in parallel said first means and said second means.

Claim 9

The apparatus as set forth in claim 7 wherein said control circuit, in the event that a routing address is stored in said second means, is further operative to abort accessing said first means.

Claim 10

The apparatus as set forth in claim 1 further comprising a plurality of interfaces wherein each one of said plurality of interfaces has an address associated therewith, said control circuit is further operative to use said addresses to communicate with said sub-networks.

Claim 11

The apparatus as set forth in claim 9 wherein said control circuit is further operative to monitor at least one of said interfaces to determine whether an address of said at least one of said interfaces changed.

Claim 12

The apparatus as set forth in claim 10 wherein said control circuit, in the event that said address of said at least one of said interfaces changed, is further operative to at least one of: delete said changed address from said second means, and update said second means to reflect said changed address.

Claim 13

The apparatus as set forth in claim 10 wherein said control circuit, in the event that said address of said at least one of said interfaces changed, is further operative to update said first means to reflect said changed address.

Claim 14

The apparatus as set forth in claim 1 wherein said timing circuit is further operative to compare said time periods with a predetermined value.

Claim 15

The apparatus as set forth in claim 13 wherein said control circuit, in response to said comparison, is further operative to at least one of delete certain address data from said second means and update said second means in response certain address data stored in said first means.

Claim 18

The method as set forth in claim 15 further including, upon a determination that a particular address is not stored in said second memory, the step of storing said particular address from said first memory in said second memory.

Claim 19

The method as set forth in claim 15 further including the steps of: accessing said second memory; and accessing said first memory in the event that a particular address is not stored in said second memory.

Claim 20

The method as set forth in claim 15 wherein said routing step is preceded by the step of accessing substantially in parallel said first memory and said second memory.

Claim 21

The method as set forth in claim 18 further including the step of aborting said first memory access in the event that a particular address is stored in said second memory.

Claim 22

The method as set forth in claim 15 further including the step of monitoring at least one of said sub-networks to determine whether any of said addresses has changed.

Claim 23

The method as set forth in claim 20 further including, in the event that at least one of said addresses has changed, one of the steps of: deleting said changed address from said second memory; and updating said second memory to reflect said changed address.

Claim 24

The method as set forth in claim 20 further including, in the event that, at least one of said addresses has changed, the step of updating said first memory to reflect said changed address.

Claim 25

The method as set forth in claim 15 further comprising the steps of: comparing said time periods with a predetermined value; and deleting, in response to said comparison, at least one address from said second memory.

Claim 26

A processing system network comprising: a plurality of sub-networks wherein each said sub-networks includes at least one node; and an apparatus for routing data packets between said plurality of sub-networks, said apparatus comprising: a first means for storing addresses for routing data packets between ones of said plurality of sub-networks; a second means, associated with said first means, for storing ones of said recently accessed addresses for use in routing ones of said data packets between particular ones of said plurality of sub-networks; a control circuit, associated with said first means and said second means, arranged to route said data packets between said plurality of sub-networks in response to said recently accessed addresses and destination indicia associated with said data packets; and a timing circuit, associated with said control circuit, that indicates time periods during which said recently accessed addresses are stored in said second means, wherein said control circuit deletes at least one recently accessed address from said second means whenever a time period associated with said least one recently accessed address exceeds a maximum value, said deletion thereby eliminating least recently accessed addresses from said second means.

Claim 27

A processing system network comprising: a plurality of sub-networks wherein each said sub-networks includes at least one node; and an apparatus for routing data packets between said plurality of sub-networks, said apparatus comprising: a first means for storing addresses for routing data packets between ones of said plurality of sub-networks; a second means, associated with said first means, for storing ones of said recently accessed addresses for use in routing ones of said data packets between particular ones of said plurality of sub-networks; a control circuit, associated with said first means and said second means, arranged to route said data packets between said plurality of sub-networks in response to said recently accessed addresses and destination indicia associated with said data packets; and a timing circuit, associated with said control circuit, that indicates time periods during which said recently accessed addresses are stored in said second means, wherein said control circuit deletes at least one recently accessed address from said second means whenever a time period associated with said least one recently accessed address exceeds a maximum value, said deletion thereby eliminating least recently accessed addresses from said second means.

Claim 28

The network as set forth in claim 24 wherein said control circuit is operative to determine whether a particular received data packet requires special processing.

Claim 29

The network as set forth in claim 25 wherein said control circuit, in the event said particular received data packet does not require special processing, is further operative to store a retrieved address from said first means in said second means.

Claim 30

The network as set forth in claim 24 wherein said control circuit is operative to access initially said second means and then said first means in the event that a particular address is not stored therein.

Claim 31

The network as set forth in claim 24 wherein said control circuit is operative to access substantially in parallel said first means and said second means.

Claim 32

The network as set forth in claim 28 wherein said control circuit, in the event that a particular address is selectively stored in said second means, is further operative to abort accessing said first means.

Claim 33

The network as set forth in claim 24 wherein said apparatus includes a plurality of interfaces, wherein ones of said plurality of interfaces have an address associated therewith, and wherein said control circuit is further operative to use ones of said addresses to communicate with ones of said plurality of sub-networks.

Claim 34

The network as set forth in claim 30 wherein said control circuit is further operative to monitor at least one of said interfaces to determine whether at least one of said addresses has changed.

Claim 35

The network as set forth in claim 31 wherein said control circuit, in response to at least one of said monitored addresses being changed, is further operative to update at least one of said first means and said second means to reflect said changed address.

Claim 36

The network as set forth in claim 24 wherein said control circuit is further operative to: compare said time periods with a predetermined value; and delete, in response to said comparison, at least one address from said second means.