Patent US5861777A successfully refreshed from Google Patents.
US5861777A
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US
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Method and apparatus for compensation of phase distortion in power amplifiers
Assignee: Google Technology Holdings LLC
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Filing: 1997-07-02
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Granted: 1999-01-19
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Expires: 2017-07-02
Abstract
Abstract A method and apparatus for efficient power amplification with low phase distortion includes an envelope detector (30), a scaling amplifier (40), a driver amplifier (50), and a power amplifier (60). The scaling amplifier (40), in response to the envelope signal from the envelope detector (30), generates a bias signal which causes predistortion in the driver amplifier (50). The predistortion in the driver amplifier (50) compensates for phase distortion in the driver amplifier (50) and the power amplifier (60), resulting in low phase distortion output. An EER-type amplifier (200) with high efficiency utilizes the predistortion of a driver amplifier (250) to compensate for phase distortion in the driver amplifier (250) and a power amplifier (260).
Inventors
- 👤 Bernard Eugene Sigmon
- 👤 Ronald Gene Myers
- 👤 Robert Michael Jackson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 20:46
CPC Classifications
H; H03; H03G; H03G3/00; H03G3/20; H03G3/30; H03G3/3036; H03G3/3042; H03F; H03F1/00; H03F1/02; H03F1/0205; H03F1/0211; H03F1/0216; H03F1/0222; H03F1/32; H03F1/3241
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
96 words
A power amplifier circuit for amplifying an input signal, said power amplifier circuit comprising: an envelope detector for producing an envelope signal from said input signal; an envelope amplifier coupled to said envelope detector for producing an amplified envelope signal; a scaling amplifier for summing said amplified envelope signal with a nominal gate bias to produce a gate bias signal; and a power amplifier for amplifying said input signal, wherein said power amplifier comprises a driver amplifier stage biased with said gate bias signal, and a final power amplifier stage modulated with said amplified envelope signal.
Claim 2
Dependent Claim
96 words
A power amplifier circuit for amplifying an input signal, said power amplifier circuit comprising: an envelope detector for producing an envelope signal from said input signal; an envelope amplifier coupled to said envelope detector for producing an amplified envelope signal; a scaling amplifier for summing said amplified envelope signal with a nominal gate bias to produce a gate bias signal; and a power amplifier for amplifying said input signal, wherein said power amplifier comprises a driver amplifier stage biased with said gate bias signal, and a final power amplifier stage modulated with said amplified envelope signal.
Claim 3
Dependent Claim
89 words
A power amplifier circuit for amplifying an input signal, said power amplifier circuit comprising: an envelope detector for producing an envelope signal from said input signal; an envelope amplifier coupled to said envelope detector for producing an amplified envelope signal, wherein said envelope amplifier comprises a class S modulators; a scaling amplifier for summing said amplified envelope signal with a nominal gate bias to produce a gate bias signal; and a power amplifier for amplifying said input signal, wherein said power amplifier is biased with said gate bias signal.
Claim 4
Dependent Claim
89 words
A power amplifier circuit for amplifying an input signal, said power amplifier circuit comprising: an envelope detector for producing an envelope signal from said input signal; an envelope amplifier coupled to said envelope detector for producing an amplified envelope signal, wherein said envelope amplifier comprises a class S modulators; a scaling amplifier for summing said amplified envelope signal with a nominal gate bias to produce a gate bias signal; and a power amplifier for amplifying said input signal, wherein said power amplifier is biased with said gate bias signal.
Claim 5
Dependent Claim
15 words
The power amplifier circuit of claim 2 wherein said scaling amplifier comprises an operational amplifier.
Claim 6
Dependent Claim
99 words
A power amplifier with reduced phase distortion, said power amplifier comprising: a driver amplifier stage which receives an input signal; a power amplifier stage having an input coupled to an output of said driver amplifier stage, and having an output for producing an output signal; a scaling amplifier for modulating a gate bias of said driver amplifier stage; an envelope detector for detecting an envelope of the input signal to produce an envelope signal, wherein said scaling amplifier is responsive to said envelope signal; and an envelope amplifier coupled to said envelope detector, for producing an amplified envelope signal.
Claim 7
Dependent Claim
99 words
A power amplifier with reduced phase distortion, said power amplifier comprising: a driver amplifier stage which receives an input signal; a power amplifier stage having an input coupled to an output of said driver amplifier stage, and having an output for producing an output signal; a scaling amplifier for modulating a gate bias of said driver amplifier stage; an envelope detector for detecting an envelope of the input signal to produce an envelope signal, wherein said scaling amplifier is responsive to said envelope signal; and an envelope amplifier coupled to said envelope detector, for producing an amplified envelope signal.
Claim 8
Dependent Claim
18 words
The power amplifier of claim 4 wherein said power amplifier stage is modulated by said amplified envelope signal.
Claim 9
Dependent Claim
15 words
The power amplifier of claim 5 wherein said envelope amplifier comprises a class S modulator.
Claim 10
Dependent Claim
97 words
A communications device comprising: a power amplifier circuit wherein said power amplifier circuit comprises: (i) a driver amplifier stage which receives an input signal; (ii) a power amplifier stage having an input coupled to an output of said driver amplifier stage, and having an output for producing an output signal; (iii) an envelope detector for detecting an envelope of the input signal to produce an envelope signal; (iv) an envelope amplifier coupled to said envelope detector, for producing an amplified envelope signal; and (v) a scaling amplifier for modulating a gate bias of said driver amplifier stage.
Claim 11
Dependent Claim
97 words
A communications device comprising: a power amplifier circuit wherein said power amplifier circuit comprises: (i) a driver amplifier stage which receives an input signal; (ii) a power amplifier stage having an input coupled to an output of said driver amplifier stage, and having an output for producing an output signal; (iii) an envelope detector for detecting an envelope of the input signal to produce an envelope signal; (iv) an envelope amplifier coupled to said envelope detector, for producing an amplified envelope signal; and (v) a scaling amplifier for modulating a gate bias of said driver amplifier stage.
Claim 12
Dependent Claim
95 words
In an EER-type amplifier which introduces phase distortion in a signal path, a method of reducing said phase distortion, said method comprising the steps of: envelope detecting an input signal to produce an envelope signal; amplifying said envelope signal to produce an amplified envelope signal; modulating a power amplifier stage with said amplified envelope signal; scaling said envelope signal to produce a scaled envelope signal; summing said scaled envelope signal with a nominal gate bias signal to produce a driver amplifier gate bias; and biasing a driver amplifier stage with said driver amplifier gate bias.
Claim 13
Dependent Claim
95 words
In an EER-type amplifier which introduces phase distortion in a signal path, a method of reducing said phase distortion, said method comprising the steps of: envelope detecting an input signal to produce an envelope signal; amplifying said envelope signal to produce an amplified envelope signal; modulating a power amplifier stage with said amplified envelope signal; scaling said envelope signal to produce a scaled envelope signal; summing said scaled envelope signal with a nominal gate bias signal to produce a driver amplifier gate bias; and biasing a driver amplifier stage with said driver amplifier gate bias.
Claim 14
Dependent Claim
39 words
The method of claim 8 wherein said amplifying step comprises: producing a pulsewidth modulated signal with a duty cycle proportional to an amplitude of said envelope signal; and filtering said pulsewidth modulated signal to produce said amplified envelope signal.
Claim 15
Dependent Claim
19 words
The power amplifier circuit of claim 1 wherein said scaling amplifier scales said amplified envelope signal prior to summing.
Claim 16
Dependent Claim
16 words
The power amplifier circuit of claim 1 wherein said envelope amplifier comprises a class S modulator.
Claim 17
Dependent Claim
15 words
The power amplifier circuit of claim 1 wherein said scaling amplifier comprises an operational amplifier.
Claim 18
Dependent Claim
19 words
The power amplifier circuit of claim 2 wherein said scaling amplifier scales said amplified envelope signal prior to summing.
Claim 19
Dependent Claim
18 words
The power amplifier circuit of claim 2 wherein said power amplifier is modulated with said amplified envelope signal.
Claim 20
Dependent Claim
21 words
The power amplifier of claim 4 wherein said scaling amplifier scales said amplified envelope signal to produce a scaled envelope signal.
Claim 21
Dependent Claim
20 words
The power amplifier of claim 15 wherein said scaling amplifier sums said scaled envelope signal and a nominal gate bias.
Claim 22
Dependent Claim
21 words
The communications device of claim 7 wherein said scaling amplifier scales said amplified envelope signal to produce a scaled envelope signal.
Claim 23
Dependent Claim
20 words
The communications device of claim 17 wherein said scaling amplifier sums said scaled envelope signal and a nominal gate bias.
References Cited (Backward Citations)
US5251330A
Cited
US5757229A
Cited
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