Process for manufacturing an interconnection substrate to connect a chip onto a reception substrate

Claim 2

Process for making an interconnection substrate to connect at least one electronic chip onto a reception substrate, the interconnection substrate having a first side with input terminals capable of being connected to the chip, and a second side, opposite the first side, with output terminals capable of being connected to the reception substrate, characterized in that this process includes the following steps: a)--forming a layer of electrically conducting meltable material on an initial substrate, b)--forming a first layer of dielectric material on the meltable layer and engraving this first dielectric layer to make openings corresponding to the interconnection substrate output terminals, c)--forming first metal blocks respectively in the openings, the blocks forming the output terminals, d)--depositing a metal layer covering the metal blocks, e)--engraving the metal layer to form conducting tracks, the tracks at least partially superposing the openings formed in the first dielectric material layer, f)--forming a second dielectric material layer covering the conducting tracks and engraving this second dielectric layer to form openings therein at least partially exposing the conducting tracks, g)--forming second metal blocks in the openings formed in the second dielectric material layer, h)--separating the first dielectric layer from the initial substrate by heating the meltable material to a temperature equal to or exceeding its melting temperature to obtain the interconnection substrate.

Claim 3

Process according to claim 1, characterized in that it further includes, between steps g) and h), a step of forming fastening studs on the second metal blocks formed in step g), the fastening studs forming the input terminals.

Claim 4

Process according to claim 1, characterized in that a tin-lead alloy is used as the electrically conducting meltable material.

Claim 5

Process according to claim 1, characterized in that the first metal blocks in step c) are formed by electrolysis, using the meltable material layer as an electrode.

Claim 6

Process according to claim 1, characterized in that during step g) the second metal blocks are formed by electrolysis using the meltable material layer in the blocks and conducting tracks as electrodes.

Claim 7

Process according to claim 1, characterized in that steps d), e), f) and g) are repeated several times.

Claim 8

Process according to claim 1, characterized in that said at least one electronic chip is connected to the interconnection substrate prior to step h).

Claim 9

Process according to claim 7, characterized in that the chip is further fixed to the substrate by means of a resin.

Claim 10

Process according to claim 1, characterized in that it further comprises a step cutting the interconnection substrate.

Claim 11

Process according to claim 1, characterized in that it further comprises, after step h), placing meltable material balls on output terminals, either directly or by means of fastening studs.

Claim 12

Process according to claim 1, characterized in that polyimide is used as the dielectric material.

Claim 13

Process according to claim 1, characterized in that copper is used to form the metal blocks in the openings and to form the conducting tracks.

Claim 14

Process for making an interconnection substrate to connect at least one electronic chip onto a reception substrate, the interconnection substrate having a first side with input terminals capable of being connected to the chip, and a second side, opposite the first side, with output terminals capable of being connected to the reception substrate, characterized in that this process includes the following steps: a)--forming a layer of electrically conducting meltable material on an initial substrate, b)--forming a first layer of dielectric material on the meltable layer and engraving this first dielectric layer to make openings corresponding to the interconnection substrate output terminals, c)--forming first metal blocks respectively in the openings, the first metal blocks forming the output terminals and being formed by electrolysis, using the meltable material layer as an electrode, d)--depositing a metal layer covering the metal blocks, e)--engraving the metal layer to form conducting tracks, the tracks at least partially superposing the openings formed in the first dielectric material layer, f)--forming a second dielectric material layer covering the conducting tracks and engraving this second dielectric layer to form openings therein at least partially exposing the conducting tracks, g)--forming second metal blocks in the openings formed in the second dielectric material layer, h)--separating the first dielectric layer from the initial substrate by heating the meltable material to a temperature equal to or exceeding its melting temperature to obtain the interconnection substrate.

Claim 15

Process for making an interconnection substrate to connect at least one electronic chip onto a reception substrate, the interconnection substrate having a first side with input terminals capable of being connected to the chip, and a second side, opposite the first side, with output terminals capable of being connected to the reception substrate, characterized in that this process includes the following steps: a)--forming a layer of electrically conducting meltable material on an initial substrate, b)--forming a first layer of dielectric material on the meltable layer and engraving this first dielectric layer to make openings corresponding to the interconnection substrate output terminals, c)--forming first metal blocks respectively in the openings, the first metal blocks forming the output terminals and being formed by electrolysis, using the meltable material layer as an electrode, d)--depositing a metal layer covering the metal blocks, e)--engraving the metal layer to form conducting tracks, the tracks at least partially superposing the openings formed in the first dielectric material layer, f)--forming a second dielectric material layer covering the conducting tracks and engraving this second dielectric layer to form openings therein at least partially exposing the conducting tracks, g)--forming second metal blocks in the openings formed in the second dielectric material layer, h)--separating the first dielectric layer from the initial substrate by heating the meltable material to a temperature equal to or exceeding its melting temperature to obtain the interconnection substrate.