US5860141A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for enabling physical memory larger than corresponding virtual memory
Assignee: Teradata US Inc
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Filing: 1996-12-11
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Granted: 1999-01-12
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Expires: 2016-12-11
Abstract
Abstract A method and apparatus for enabling a physical memory larger than a corresponding virtual memory. An apparatus is disclosed that includes a processor having an address word of a predefined length, a main memory having a size larger than the addressable range of the predefined address word, and virtual memory logic for configuring the processor virtual memory to contain a subset of the main memory as resident memory and pointers to the remainder of main memory. Analogous method steps are disclosed as is dividing main memory into a plurality of buffer uniquely identifiable within the address range of the predefined address word.
Inventors
- 👤 Peter Washington
- 👤 John H. Waters
- 👤 Richard R. Barton
- 👤 Vernon K. Boland
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 09:54
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/0223; G06F12/0292; G06F12/08; G06F12/10; G06F12/1027; G06F12/1036; G06F12/109; G06F12/06; G06F12/0615; G06F12/0623
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
118 words
A method of allocating memory, comprising the steps of: providing a processor having an address word length of a predefined size; providing a main memory having a size larger than the addressable range of said predefined address word for storing data for use by a process running in said processor; dividing said main memory into a plurality of buffers, each uniquely identifiable within the addressable range of said predefined address word; creating a unique identifier for a number of said buffers which when multiplied by buffer size equals a memory size larger than the addressable range of said predefined address word; and providing said unique identifiers in the virtual address space of a process running in said processor.
Claim 2
Independent Claim
118 words
A method of allocating memory, comprising the steps of: providing a processor having an address word length of a predefined size; providing a main memory having a size larger than the addressable range of said predefined address word for storing data for use by a process running in said processor; dividing said main memory into a plurality of buffers, each uniquely identifiable within the addressable range of said predefined address word; creating a unique identifier for a number of said buffers which when multiplied by buffer size equals a memory size larger than the addressable range of said predefined address word; and providing said unique identifiers in the virtual address space of a process running in said processor.
Claim 3
Dependent Claim
49 words
The method of claim 1, further comprising the steps of: creating a unique structure including a measure field and a flag field for each buffer for which a unique identifier was created; and providing said unique structures in the virtual address space of a process running in said processor.
Claim 4
Dependent Claim
54 words
The method of claim 1, further comprising the steps of: defining a subset of said buffers that are mapped to the virtual address space of a process running in said processor; and defining a subset of said buffers that are not mapped to the virtual address space of a process running in said processor.
Claim 5
Dependent Claim
21 words
The method of claim 3, further comprising the step of creating a list of mapped buffers that are least recently used.
Claim 6
Dependent Claim
50 words
The method of claim 4, further comprising the step of switching a requested not mapped buffer with a mapped buffer in said list of least recently used mapped buffers such that after switching the previously not mapped buffer is now mapped and the previously mapped buffer is now not mapped.
Claim 7
Dependent Claim
70 words
The method of claim 4, wherein said defining step comprises the steps of: further defining said mapped buffers to comprise Active and Inactive buffers, said Active buffers defined as those buffers that are in use by a process in said processor and said Inactive buffers defined as those buffers that are not in use by a process in said processor; and placing Inactive buffers in said least recently used list.
Claim 8
Dependent Claim
39 words
The method of claim 1, wherein said step of creating a unique identifier includes the step of making a call to a library function which operates at an interface between an application and the operating system in said processor.
Claim 9
Independent Claim
77 words
An apparatus for processing electronic data, comprising: a processor having an address word of a predefined length; a main memory having a size larger than the addressable range of said predefined address word; and virtual memory logic for configuring a virtual memory of said processor to have an address range addressable by said predefined address word and to contain a subset of said main memory as resident memory and pointers to the remainder of said main memory.
Claim 10
Independent Claim
77 words
An apparatus for processing electronic data, comprising: a processor having an address word of a predefined length; a main memory having a size larger than the addressable range of said predefined address word; and virtual memory logic for configuring a virtual memory of said processor to have an address range addressable by said predefined address word and to contain a subset of said main memory as resident memory and pointers to the remainder of said main memory.
Claim 11
Dependent Claim
35 words
The apparatus of claim 8, further comprising means for switching a portion of said resident memory with a portion of the remaining memory when that portion of the remaining memory is requested by said processor.
Claim 12
Dependent Claim
42 words
The apparatus of claim 8, further comprising: means for designating a portion of the resident memory that is least recently used; and means for switching a requested portion of the remaining memory with a least recently used portion of the resident memory.
Claim 13
Dependent Claim
39 words
The apparatus of claim 8, wherein said main memory is divided into a plurality of buffers, each buffer uniquely identifiable within the predefined address word and said virtual memory logic provides a unique pointer to each of said buffers.
Claim 14
Dependent Claim
18 words
The apparatus of claim 11, wherein each of said pointers includes fields for linking to the other pointers.
Claim 15
Dependent Claim
27 words
The apparatus of claim 11, wherein each of said plurality of buffers is of an equal size and that size is a multiple of a page size.
Claim 16
Dependent Claim
31 words
The apparatus of claim 11, further comprising a unique structure for each buffer that contains a measure field, a flag field and pointers to the unique structures of the other buffers.
Claim 17
Dependent Claim
40 words
The apparatus of claim 8, wherein said virtual memory logic includes library level logic configured to function at an interface of an operating system in said processor and an application for allocating the resident and non-resident memory to that application.
Claim 18
Dependent Claim
54 words
The apparatus of claim 11, further comprising: means for designating buffers in the resident memory as Active and Inactive, the Inactive designation indicating that a resident buffer is not currently being accessed by a process running in said processor; and means for switching a requested buffer from the remaining memory with an Inactive buffer.
Claim 19
Independent Claim
56 words
An apparatus for processing electronic data, comprising: a processor having an address word of a predefined length; a main memory having a size larger than the addressable range of said predefined address word; and means for dividing said main memory into a plurality of buffers, uniquely identifiable within the address range of said predefined address word.
Claim 20
Independent Claim
56 words
An apparatus for processing electronic data, comprising: a processor having an address word of a predefined length; a main memory having a size larger than the addressable range of said predefined address word; and means for dividing said main memory into a plurality of buffers, uniquely identifiable within the address range of said predefined address word.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-11 | 2002-07-13 | 2003-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-11 | 2006-07-13 | 2007-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-11 | 2010-07-13 | 2011-01-12 | $7700.00 | Window Closed / Lapsed |