US5749084A
Expired / Lapsed
US
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Address generation unit with segmented addresses in a microprocessor
Assignee: Intel Corp
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Filing: 1996-04-17
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Granted: 1998-05-05
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Expires: 2016-04-17
Abstract
Abstract A processor having an address generation unit (AGU) for generating an address corresponding to an entry that is to be fetched. The AGU includes a segment register file for storing address segments, and a circuit for rearranging noncontiguous base and limit bit positions of a first address segment in order to generate a second address segment having all base and limit bits in a contiguous order. The AGU further includes a circuit for executing a single microinstruction to perform read and write operations on a selected field of the second address segments stored in the segment register file.
Inventors
- 👤 Kamla P. Huck
- 👤 Scott D. Rodgers
- 👤 Andrew F. Glew
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 20:03
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/1036; G06F12/0223; G06F12/0292
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
140 words
A processor comprising: a bus; a memory; an execution unit coupled to said bus for performing arithmetic functions; a fetch unit coupled to said bus for determining an entry is to be accessed; an issue unit coupled to said bus for accessing said entry from storage in said memory; and an address generation unit (AGU) coupled to said bus for generating an address corresponding to said entry, said AGU including a segment register file for storing address segments, a circuit for rearranging noncontiguous base and limit bit positions of a first address segment in order to generate a second address segment having all base and limit bits in a contiguous order, and a circuit for executing a single microinstruction to perform read and write operations on a selected field of said second address segments stored in said segment register file.
Claim 2
Dependent Claim
140 words
A processor comprising: a bus; a memory; an execution unit coupled to said bus for performing arithmetic functions; a fetch unit coupled to said bus for determining an entry is to be accessed; an issue unit coupled to said bus for accessing said entry from storage in said memory; and an address generation unit (AGU) coupled to said bus for generating an address corresponding to said entry, said AGU including a segment register file for storing address segments, a circuit for rearranging noncontiguous base and limit bit positions of a first address segment in order to generate a second address segment having all base and limit bits in a contiguous order, and a circuit for executing a single microinstruction to perform read and write operations on a selected field of said second address segments stored in said segment register file.
Claim 3
Dependent Claim
28 words
The processor of claim 1, wherein said circuit rearranges said first address segment when said first address segment is loaded from said memory into said segment register file.
Claim 4
Dependent Claim
25 words
The processor of claim 1, wherein said AGU performs read and write operations of an entire address segment entry stored in said segment register file.
Claim 5
Dependent Claim
13 words
The processor of claim 1, wherein said selected field is a selector field.
Claim 6
Dependent Claim
13 words
The processor of claim 1, wherein said selected field is a base field.
Claim 7
Dependent Claim
13 words
The processor of claim 1, wherein said selected field is a limit field.
Claim 8
Dependent Claim
29 words
The processor of claim 6, wherein a read of said limit field causes said value to be scaled based on a granularity bit stored in said segment register file.
Claim 9
Dependent Claim
15 words
The processor of claim 1, wherein said selected field is a descriptor privilege level field.
Claim 10
Dependent Claim
38 words
The processor of claim 1, wherein said selected field is an access rights field which includes an access rights byte, a granularity bit, and a data size bit of an address segment stored in said segment register file.
Claim 11
Independent Claim
163 words
An apparatus comprising: a bus means for transmitting digital signals; a memory means coupled to said bus means for storing information; an execution means coupled to said bus means for performing arithmetic functions; a fetch means coupled to said bus means for determining an entry to be accessed; an issue means coupled to said bus means for accessing said entry from storage in said memory means; and an address generation means coupled to said bus means for generating an address corresponding to said entry, said address generation means comprising a segment register means for storing address segments and an arrangement means for rearranging noncontiguous base and limit bits of a first address segment, thereby producing a second address segment having all base and limit bits in a contiguous order, said address generation means further including a means for executing a single microinstruction to perform read and write operations on a selected field of said second address segment stored in said segment register means.
Claim 12
Independent Claim
163 words
An apparatus comprising: a bus means for transmitting digital signals; a memory means coupled to said bus means for storing information; an execution means coupled to said bus means for performing arithmetic functions; a fetch means coupled to said bus means for determining an entry to be accessed; an issue means coupled to said bus means for accessing said entry from storage in said memory means; and an address generation means coupled to said bus means for generating an address corresponding to said entry, said address generation means comprising a segment register means for storing address segments and an arrangement means for rearranging noncontiguous base and limit bits of a first address segment, thereby producing a second address segment having all base and limit bits in a contiguous order, said address generation means further including a means for executing a single microinstruction to perform read and write operations on a selected field of said second address segment stored in said segment register means.
Claim 13
Dependent Claim
28 words
The apparatus of claim 10, wherein said arrangement means rearranges said first address segment upon loading said first address segment into said segment register means from said memory.
Claim 14
Dependent Claim
27 words
The apparatus of claim 10, wherein said address generation means performs read and write operations of an entire address segment entry stored in said segment register means.
Claim 15
Dependent Claim
13 words
The apparatus of claim 10, wherein said selected field is a selector field.
Claim 16
Dependent Claim
13 words
The apparatus of claim 10, wherein said selected field is a base field.
Claim 17
Dependent Claim
40 words
The apparatus of claim 10, wherein said selected field is a limit field, a read of said limit field causing a value resident in said field to be scaled based on a granularity bit stored in said segment register means.
Claim 18
Dependent Claim
14 words
The apparatus of claim 10, wherein said selected field is a descriptor privilege level.
Claim 19
Dependent Claim
37 words
The apparatus of claim 10, wherein said field is an access rights field which includes an access rights byte, a granularity bit, and a data size bit of an address segment stored in said segment register means.
Claim 20
Dependent Claim
164 words
A computer system comprising: a bus; a main memory coupled to said bus, said main memory storing data; a microprocessor coupled to said bus for processing said data, said microprocessor comprising: a memory; an execution unit coupled to said bus for performing arithmetic functions; a fetch unit coupled to said bus for determining an entry to be accessed; an issue unit coupled to said bus for accessing said entry from storage in said memory; an address generation unit (AGU) coupled to said bus for generating an address corresponding to said entry, said AGU includes a segment register file for storing address segments, a circuit for rearranging noncontiguous base and limit bit positions of a first address segment in order to generate a second address segment having all base and limit bits in a contiguous order, and a circuit for executing a single microinstruction to perform read and write operations of a selected field of said second address segment stored in said segment register file.
Claim 21
Dependent Claim
164 words
A computer system comprising: a bus; a main memory coupled to said bus, said main memory storing data; a microprocessor coupled to said bus for processing said data, said microprocessor comprising: a memory; an execution unit coupled to said bus for performing arithmetic functions; a fetch unit coupled to said bus for determining an entry to be accessed; an issue unit coupled to said bus for accessing said entry from storage in said memory; an address generation unit (AGU) coupled to said bus for generating an address corresponding to said entry, said AGU includes a segment register file for storing address segments, a circuit for rearranging noncontiguous base and limit bit positions of a first address segment in order to generate a second address segment having all base and limit bits in a contiguous order, and a circuit for executing a single microinstruction to perform read and write operations of a selected field of said second address segment stored in said segment register file.
Claim 22
Dependent Claim
29 words
The computer system of claim 18, wherein said circuit rearranges said first address segment when said first address segment is loaded into said segment register file from said memory.
Claim 23
Dependent Claim
26 words
The computer system of claim 18, wherein said AGU performs read and write operations of an entire address segment entry stored in said segment register file.
Claim 24
Dependent Claim
14 words
The computer system of claim 18, wherein said selected field is a selector field.
Claim 25
Dependent Claim
14 words
The computer system of claim 18, wherein said selected field is a base field.
Claim 26
Dependent Claim
42 words
The computer system of claim 18, wherein said selected field is a limit field, a read of said limit field causing a value resident in said limit field to be scaled based on a granularity bit stored in said segment register file.
Claim 27
Dependent Claim
16 words
The computer system of claim 18, wherein said selected field is a descriptor privilege level field.
Claim 28
Dependent Claim
39 words
The computer system of claim 18, wherein said selected field is an access rights field which includes an access rights byte, a granularity bit, and a data size bit of an address segment stored in said segment register file.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-04 | 2001-11-03 | 2002-05-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-04 | 2005-11-03 | 2006-05-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-04 | 2009-11-03 | 2010-05-05 | $7700.00 | Window Closed / Lapsed |