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Patent US5859989A successfully refreshed from Google Patents.
US5859989A
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US
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Apparatus method and system for 64 bit peripheral component interconnect bus using accelerated graphics port logic circuits
Assignee: Hewlett Packard Development Co LP
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Filing: 1997-05-13
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Granted: 1999-01-12
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Expires: 2017-05-13
Abstract
Abstract A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between a 64 bit additional peripheral component interconnect ("PCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional PCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional 64 bit PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request ("REQ") and Grant ("GNT") signal lines for each PCI device utilized on the additional 64 bit PCI bus. Selection of the type of bus bridge (AGP or PCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of a PCI device connected to the common bus.
Inventors
- 👤 Sompong Paul Olarig
- 👤 Ronald Timothy Horan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:02
CPC Classifications
G; G06; G06T; G06T11/00
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
170 words
A computer system having a core logic chip set configurable for either an accelerated graphics port (AGP) bus or an additional peripheral component interconnect (PCI) bus, said system comprising: a central processing unit connected to a host bus; a random access memory connected to a random access memory bus; a core logic chip set connected to the host bus and the random access memory bus; said core logic chip set configured as a first interface bridge between the host bus and the random access memory bus, a second interface bridge between the host bus and a first peripheral component interconnect bus, and a third interface bridge between the random access memory bus and the first peripheral component interconnect bus; said core logic chip set configured as a fourth interface bridge between the host bus and a second 64 bit peripheral component interconnect bus; and said core logic chip set configured as a fifth interface bridge between the random access memory bus and the second 64 bit peripheral component interconnect bus.
Claim 2
Dependent Claim
170 words
A computer system having a core logic chip set configurable for either an accelerated graphics port (AGP) bus or an additional peripheral component interconnect (PCI) bus, said system comprising: a central processing unit connected to a host bus; a random access memory connected to a random access memory bus; a core logic chip set connected to the host bus and the random access memory bus; said core logic chip set configured as a first interface bridge between the host bus and the random access memory bus, a second interface bridge between the host bus and a first peripheral component interconnect bus, and a third interface bridge between the random access memory bus and the first peripheral component interconnect bus; said core logic chip set configured as a fourth interface bridge between the host bus and a second 64 bit peripheral component interconnect bus; and said core logic chip set configured as a fifth interface bridge between the random access memory bus and the second 64 bit peripheral component interconnect bus.
Claim 3
Dependent Claim
18 words
The computer system of claim 1, wherein the central processing unit is a plurality of central processing units.
Claim 4
Dependent Claim
18 words
The computer system of claim 1, wherein the core logic chip set is at least one integrated circuit.
Claim 5
Dependent Claim
25 words
The computer system of claim 3, wherein the at least one integrated circuit core logic chip set is at least one application specific integrated circuit.
Claim 6
Dependent Claim
26 words
The computer system of claim 3, wherein the at least one integrated circuit core logic chip set is at least one programmable logic array integrated circuit.
Claim 7
Dependent Claim
36 words
The computer system of claim 1, further comprising at least one peripheral component interconnect device capable of running at 66 megahertz and connected to the second 64 bit peripheral component interconnect bus running at 66 megahertz.
Claim 8
Dependent Claim
36 words
The computer system of claim 1, further comprising at least one peripheral component interconnect device capable of running at 33 megahertz and connected to the second 64 bit peripheral component interconnect bus running at 33 megahertz.
Claim 9
Dependent Claim
35 words
The computer system of claim 1, wherein the host bus, random access memory bus, first peripheral component interconnect bus, and second 64 bit peripheral component interconnect bus are on a computer system printed circuit board.
Claim 10
Dependent Claim
50 words
The computer system of claim 8, wherein the fourth and fifth interface bridges of said core logic chip set are configured for the second 64 bit peripheral component interconnect bus by an electrical signal sent from a hardwired jumper circuit located on the printed circuit board of the computer system.
Claim 11
Dependent Claim
31 words
The computer system of claim 8, wherein at least one peripheral component interconnect connector is on the printed circuit board and connected to the second 64 bit peripheral component interconnect bus.
Claim 12
Dependent Claim
39 words
The computer system of claim 1, wherein the fourth and fifth interface bridges of said core logic chip set are configured for the second 64 bit peripheral component interconnect bus by software control of said core logic chip set.
Claim 13
Dependent Claim
38 words
The computer system of claim 11, wherein the fourth and fifth interface bridges of said core logic chip set are configured for the second 64 bit peripheral component interconnect bus when a peripheral component interconnect device is detected.
Claim 14
Dependent Claim
25 words
The computer system of claim 12, wherein configuration of said core logic chip set is done during power on self test of the computer system.
Claim 15
Dependent Claim
22 words
The computer system of claim 12, wherein configuration of said core logic chip set is done during configuration of the computer system.
Claim 16
Independent Claim
185 words
A method, in a computer system, of configuring a core logic chip set for either an accelerated graphics port (AGP) bus or an additional peripheral component interconnect (PCI) bus, said method comprising the steps of: providing a central processing unit connected to a host bus, providing a random access memory connected to a random access memory bus; providing a core logic chip set connected to the host bus and the random access memory bus; configuring said core logic chip set as a first interface bridge between the host bus and the random access memory bus, a second interface bridge between the host bus and a first peripheral component interconnect bus, and a third interface bridge between the random access memory bus and the first peripheral component interconnect bus; and configuring said core logic chip set as a fourth interface bridge between the host bus and a second 64 bit peripheral component interconnect bus and a fifth interface bridge between the random access memory bus and the second 64 bit peripheral component interconnect bus when a configuration signal is applied to said core logic chip set.
Claim 17
Independent Claim
185 words
A method, in a computer system, of configuring a core logic chip set for either an accelerated graphics port (AGP) bus or an additional peripheral component interconnect (PCI) bus, said method comprising the steps of: providing a central processing unit connected to a host bus, providing a random access memory connected to a random access memory bus; providing a core logic chip set connected to the host bus and the random access memory bus; configuring said core logic chip set as a first interface bridge between the host bus and the random access memory bus, a second interface bridge between the host bus and a first peripheral component interconnect bus, and a third interface bridge between the random access memory bus and the first peripheral component interconnect bus; and configuring said core logic chip set as a fourth interface bridge between the host bus and a second 64 bit peripheral component interconnect bus and a fifth interface bridge between the random access memory bus and the second 64 bit peripheral component interconnect bus when a configuration signal is applied to said core logic chip set.
Claim 18
Dependent Claim
34 words
The method of claim 15, wherein the configuration signal is applied to said core logic chip set when a peripheral component interconnect device is detected on the second 64 bit peripheral component interconnect bus.
Claim 19
Dependent Claim
23 words
The method of claim 16, wherein the peripheral component interconnect device is detected during a power on self test of the computer system.
Claim 20
Dependent Claim
20 words
The method of claim 16, wherein the peripheral component interconnect device is detected during a configuration of the computer system.
Claim 21
Dependent Claim
168 words
A core logic chip set configurable for either an accelerated graphics port (AGP) bus or an additional peripheral component interconnect (PCI) bus, comprising: a core logic chip set adapted for connection to a central processing unit host bus, random access memory bus, a first peripheral component interconnect bus, and an accelerated graphics port bus or a second peripheral 64 bit component interconnect bus; said core logic chip set configured as a first interface bridge between the host bus and the random access memory bus, a second interface bridge between the host bus and the first peripheral component interconnect bus, and a third interface bridge between the random access memory bus and the first peripheral component interconnect bus; said core logic chip set configured as a fourth interface bridge between the host bus and the second 64 bit peripheral component interconnect bus; and said core logic chip set configured as a fifth interface bridge between the random access memory bus and the second 64 bit peripheral component interconnect bus.
Claim 22
Dependent Claim
168 words
A core logic chip set configurable for either an accelerated graphics port (AGP) bus or an additional peripheral component interconnect (PCI) bus, comprising: a core logic chip set adapted for connection to a central processing unit host bus, random access memory bus, a first peripheral component interconnect bus, and an accelerated graphics port bus or a second peripheral 64 bit component interconnect bus; said core logic chip set configured as a first interface bridge between the host bus and the random access memory bus, a second interface bridge between the host bus and the first peripheral component interconnect bus, and a third interface bridge between the random access memory bus and the first peripheral component interconnect bus; said core logic chip set configured as a fourth interface bridge between the host bus and the second 64 bit peripheral component interconnect bus; and said core logic chip set configured as a fifth interface bridge between the random access memory bus and the second 64 bit peripheral component interconnect bus.
Claim 23
Dependent Claim
32 words
The core logic chip set according to claim 19, wherein the fourth and fifth interface bridges are configured by a hardware jumper applying a control signal to said core logic chip set.
Claim 24
Dependent Claim
30 words
The core logic chip set according to claim 19, wherein the fourth and fifth interface bridges are configured by software configuring a control register in said core logic chip set.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-11 | 2002-07-13 | 2003-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-11 | 2006-07-13 | 2007-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-11 | 2010-07-13 | 2011-01-12 | $7700.00 | Window Closed / Lapsed |