US5858829A
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Method for fabricating dynamic random access memory (DRAM) cells with minimum active cell areas using sidewall-spacer bit lines
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1998-06-29
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Granted: 1999-01-12
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Expires: 2018-06-29
Abstract
Abstract A method for making DRAM cells with minimum active device areas (cell areas) using novel sidewall-spacer bit lines is achieved. A trench is etched in an insulating layer aligned over the device areas and orthogonal to the gate electrodes, and extending over the first and second source/drain areas. A conducting layer is deposited and etched back to form sidewall-spacer bit lines. A planar second insulating layer is formed in which bit line contact openings are etched between the sidewall-spacer bit lines to the first source/drain areas. The contact openings are filled with a third conducting layer to form the bit line contacts. A third insulating layer is deposited and capacitor node contact openings are etched between the sidewall-spacer bit lines and to the second source/drain areas. An insulating layer is deposited and etched back to insulate the sidewall-spacer bit lines in the node contact openings and a fourth con-ducting layer is deposited and etched back to form the node contacts. By this self-aligned method, the minimum unit cell area (device area) can be reduced to about 6F 2 , where F is the minimum feature size for the current technology. Any one of the current stacked capacitor structures, such as crown, fin-shaped, and the like, can now be built on the node contacts to provide memory cells with increased packing density.
Inventors
- 👤 Li Yeat Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:07
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/30; H10B12/31
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
356 words
A method for fabricating dynamic random access memory (DRAM) cells with minimum memory cell areas on a semiconductor substrate, comprising the steps of: providing a semiconductor substrate having said memory cell areas surrounded by field oxide regions; depositing and patterning a first electrically conducting layer and form word lines extending over said cell areas to form gate electrodes for field effect transistors, and further forming first and second source/drain areas, one on each side and adjacent to said gate electrodes; depositing and planarizing a first insulating layer on said substrate; forming trenches in said first insulating layer aligned over said cell areas and orthogonal to said gate electrodes and aligned and extending over said first and second source/drain areas using a photoresist mask and anisotropically plasma etching; depositing a conformal second conducting layer on said first insulating layer and anisotropically etching back to form sidewall-spacer bit lines on sidewalls of said trenches; depositing a second insulating layer sufficiently thick to fill said trenches between said sidewall-spacer bit lines and providing a planar surface; anisotropically etching bit line contact openings in said second and said first insulating layers aligned over and between said sidewall-spacer bit lines and etched to said first source/drain areas; depositing a third conducting layer to fill said bit line contact openings and selectively removing said third conducting layer on a surface of said second insulating layer to form bit line contacts to said first source/drain areas and contacting said sidewall-spacer bit lines exposed in said bit line contact openings; depositing a third insulating layer; anisotropically etching openings in said third, second and first insulating layers aligned over and between said sidewall-spacer bit lines and to said second source/drain areas to form capacitor node contact openings; depositing a conformal fourth insulating layer in said node contact openings and anisotropically etching back to form insulating sidewalls on any exposed sidewall-spacer bit lines in said node contact openings; depositing a fourth conducting layer to fill said node contact openings to form node contacts to said second source/drain areas; and forming stacked capacitors to complete said dynamic random access memory (DRAM) cells with minimum memory cell areas.
Claim 2
Independent Claim
356 words
A method for fabricating dynamic random access memory (DRAM) cells with minimum memory cell areas on a semiconductor substrate, comprising the steps of: providing a semiconductor substrate having said memory cell areas surrounded by field oxide regions; depositing and patterning a first electrically conducting layer and form word lines extending over said cell areas to form gate electrodes for field effect transistors, and further forming first and second source/drain areas, one on each side and adjacent to said gate electrodes; depositing and planarizing a first insulating layer on said substrate; forming trenches in said first insulating layer aligned over said cell areas and orthogonal to said gate electrodes and aligned and extending over said first and second source/drain areas using a photoresist mask and anisotropically plasma etching; depositing a conformal second conducting layer on said first insulating layer and anisotropically etching back to form sidewall-spacer bit lines on sidewalls of said trenches; depositing a second insulating layer sufficiently thick to fill said trenches between said sidewall-spacer bit lines and providing a planar surface; anisotropically etching bit line contact openings in said second and said first insulating layers aligned over and between said sidewall-spacer bit lines and etched to said first source/drain areas; depositing a third conducting layer to fill said bit line contact openings and selectively removing said third conducting layer on a surface of said second insulating layer to form bit line contacts to said first source/drain areas and contacting said sidewall-spacer bit lines exposed in said bit line contact openings; depositing a third insulating layer; anisotropically etching openings in said third, second and first insulating layers aligned over and between said sidewall-spacer bit lines and to said second source/drain areas to form capacitor node contact openings; depositing a conformal fourth insulating layer in said node contact openings and anisotropically etching back to form insulating sidewalls on any exposed sidewall-spacer bit lines in said node contact openings; depositing a fourth conducting layer to fill said node contact openings to form node contacts to said second source/drain areas; and forming stacked capacitors to complete said dynamic random access memory (DRAM) cells with minimum memory cell areas.
Claim 3
Dependent Claim
39 words
The method of claim 1, wherein said first conductive layer is a polycide layer consisting of a conductively doped polysilicon layer and a refractory metal silicide layer and has a total thickness of between about 1000 and 3000 Angstroms.
Claim 4
Dependent Claim
30 words
The method of claim 1, wherein said first insulating layer is silicon oxide and has a thickness after planarizing of between about 3000 and 6000 Angstroms over said word lines.
Claim 5
Dependent Claim
25 words
The method of claim 1, wherein said trenches in said first insulating layer are etched to a depth of between about 500 and 2000 Angstroms.
Claim 6
Dependent Claim
26 words
The method of claim 1, wherein said trenches have a width of less than 2F, where F is a minimum feature size of said photoresist mask.
Claim 7
Dependent Claim
29 words
The method of claim 1, wherein said second conducting layer is an N + doped polysilicon and is deposited to a thickness of between about 600 and 1600 Angstroms.
Claim 8
Dependent Claim
15 words
The method of claim 1, wherein said second insulating layer is a borophosphosilicate glass (BPSG).
Claim 9
Dependent Claim
14 words
The method of claim 1, wherein said second insulating layer is a spin-on-glass (SOG).
Claim 10
Dependent Claim
32 words
The method of claim 1, wherein said third conducting layer is an in-situ N + doped polysilicon layer and is deposited to a thickness sufficient to fill said bit line contact openings.
Claim 11
Dependent Claim
49 words
The method of claim 1, wherein said third insulating layer is composed of a borophosphosilicate glass (BPSG) deposited to a thickness of between about 500 and 3000 Angstroms, and having on a top surface a silicon nitride etch-stop layer having a thickness of between about 60 and 200 Angstroms.
Claim 12
Dependent Claim
25 words
The method of claim 1, wherein said conformal fourth insulating layer is silicon nitride deposited to a thickness of between about 100 and 300 Angstroms.
Claim 13
Dependent Claim
31 words
The method of claim 1, wherein said fourth conducting layer is an in-situ N + doped polysilicon layer and is deposited to a thickness sufficient to fill said node contact openings.
Claim 14
Independent Claim
376 words
A method for fabricating dynamic random access memory (DRAM) cells with minimum memory cell areas on a semiconductor substrate, comprising the steps of: providing a semiconductor substrate having said memory cell areas surrounded by field oxide regions; depositing and patterning a first electrically conducting layer, composed of a doped polysilicon, and forming word lines extending over said cell areas to form gate electrodes for field effect transistors, and further forming first and second source/drain areas, one on each side and adjacent to said gate electrodes; depositing and planarizing a first insulating layer on said substrate; forming trenches in said first insulating layer aligned over said cell areas and orthogonal to said gate electrodes and aligned and extending over said first and second source/drain areas using a photoresist mask and anisotropically plasma etching; depositing a conformal second conducting layer, composed of a doped polysilicon, on said first insulating layer and anisotropically etching back to form sidewall-spacer bit lines on sidewalls of said trenches; depositing a second insulating layer sufficiently thick to fill said trenches between said sidewall-spacer bit lines and providing a planar surface; anisotropically etching bit line contact openings in said second and said first insulating layers aligned over and between said sidewall-spacer bit lines and etched to said first source/drain areas; depositing a third conducting layer, composed of a doped polysilicon, to fill said bit line contact openings and selectively removing said third conducting layer on a surface of said second insulating layer to form bit line contacts to said first source/drain areas and contacting said sidewall-spacer bit lines exposed in said bit line contact openings; depositing a third insulating layer; anisotropically etching openings in said third, second and first insulating layers aligned over and between said sidewall-spacer bit lines and to said second source/drain areas to form capacitor node contact openings; depositing a conformal fourth insulating layer in said node contact openings and anisotropically etching back to form insulating sidewalls on any exposed sidewall-spacer bit lines in said node contact openings; depositing a fourth conducting layer, composed of a doped polysilicon, to fill said node contact openings to form node contacts to said second source/drain areas; and forming stacked capacitors to complete said dynamic random access memory (DRAM) cells with minimum memory cell areas.
Claim 15
Independent Claim
376 words
A method for fabricating dynamic random access memory (DRAM) cells with minimum memory cell areas on a semiconductor substrate, comprising the steps of: providing a semiconductor substrate having said memory cell areas surrounded by field oxide regions; depositing and patterning a first electrically conducting layer, composed of a doped polysilicon, and forming word lines extending over said cell areas to form gate electrodes for field effect transistors, and further forming first and second source/drain areas, one on each side and adjacent to said gate electrodes; depositing and planarizing a first insulating layer on said substrate; forming trenches in said first insulating layer aligned over said cell areas and orthogonal to said gate electrodes and aligned and extending over said first and second source/drain areas using a photoresist mask and anisotropically plasma etching; depositing a conformal second conducting layer, composed of a doped polysilicon, on said first insulating layer and anisotropically etching back to form sidewall-spacer bit lines on sidewalls of said trenches; depositing a second insulating layer sufficiently thick to fill said trenches between said sidewall-spacer bit lines and providing a planar surface; anisotropically etching bit line contact openings in said second and said first insulating layers aligned over and between said sidewall-spacer bit lines and etched to said first source/drain areas; depositing a third conducting layer, composed of a doped polysilicon, to fill said bit line contact openings and selectively removing said third conducting layer on a surface of said second insulating layer to form bit line contacts to said first source/drain areas and contacting said sidewall-spacer bit lines exposed in said bit line contact openings; depositing a third insulating layer; anisotropically etching openings in said third, second and first insulating layers aligned over and between said sidewall-spacer bit lines and to said second source/drain areas to form capacitor node contact openings; depositing a conformal fourth insulating layer in said node contact openings and anisotropically etching back to form insulating sidewalls on any exposed sidewall-spacer bit lines in said node contact openings; depositing a fourth conducting layer, composed of a doped polysilicon, to fill said node contact openings to form node contacts to said second source/drain areas; and forming stacked capacitors to complete said dynamic random access memory (DRAM) cells with minimum memory cell areas.
Claim 16
Dependent Claim
36 words
The method of claim 13, wherein said polycide consisting of a conductively doped polysilicon layer with a top layer of tungsten silicide and said polycide has a total thickness of between about 1000 and 3000 Angstroms.
Claim 17
Dependent Claim
30 words
The method of claim 13, wherein said first insulating layer is silicon oxide and has a thickness after planarizing of between about 3000 and 6000 Angstroms over said word lines.
Claim 18
Dependent Claim
25 words
The method of claim 13, wherein said trenches in said first insulating layer are etched to a depth of between about 500 and 2000 Angstroms.
Claim 19
Dependent Claim
26 words
The method of claim 13, wherein said trenches have a width of less than 2F, where F is a minimum feature size of said photoresist mask.
Claim 20
Dependent Claim
33 words
The method of claim 13, wherein said second conducting layer, composed of polysilicon, is in-situ doped with an N-type dopant and is deposited to a thickness of between about 600 and 1600 Angstroms.
Claim 21
Dependent Claim
15 words
The method of claim 13, wherein said second insulating layer is a borophosphosilicate glass (BPSG).
Claim 22
Dependent Claim
14 words
The method of claim 13, wherein said second insulating layer is a spin-on-glass (SOG).
Claim 23
Dependent Claim
35 words
The method of claim 13, wherein said third conducting layer, composed of a polysilicon, is in-situ doped with an N-type dopant, and is deposited to a thickness sufficient to fill said bit line contact openings.
Claim 24
Dependent Claim
49 words
The method of claim 13, wherein said third insulating layer is composed of a borophosphosilicate glass (BPSG) deposited to a thickness of between about 500 and 3000 Angstroms, and having on a top surface a silicon nitride etch-stop layer having a thickness of between about 60 and 200 Angstroms.
Claim 25
Dependent Claim
25 words
The method of claim 13, wherein said conformal fourth insulating layer is silicon nitride deposited to a thickness of between about 100 and 300 Angstroms.
Claim 26
Dependent Claim
33 words
The method of claim 12, wherein said fourth conducting layer, composed of polysilicon, is in-situ doped with an N-type dopant, and is deposited to a thickness sufficient to fill said node contact openings.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-01-11 | 2002-07-13 | 2003-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-11 | 2006-07-13 | 2007-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-11 | 2010-07-13 | 2011-01-12 | $7700.00 | Window Closed / Lapsed |