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US5856985A
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Test pattern generator
Assignee: Advantest Corp
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Filing: 1996-12-01
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Granted: 1999-01-05
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Expires: 2016-12-01
Abstract
Abstract A test pattern generator is provided that can perform a block write function testing at high speed. To achieve this aim, a data register 41 is provided which takes in data signal from a data generator 13 by a first write signal from a control signal generator 15. An address selector 44 is provided which takes in specific bits from an address generated by an address generator 12. A mask data register file 42 is provided which takes the data signal in an area specified by a second write signal from a control signal generator 15. A write data register file 43 is provided which takes the data signal in an area specified by a third write signal from the control signal generator 15. A data formatter 60 is provided that synthesizes and outputs either an output data of the data register 41 or an output data of the data generator 13 based on the above signals. Those components described above comprise the test pattern generator.
Inventors
- 👤 Kenichi Fujisaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 04:36
CPC Classifications
G; G11; G11C; G11C29/00; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/31813; G01R31/319; G01R31/31917; G01R31/31919; G01R31/31928; G11C29/04; G11C29/08; G11C29/12; G11C29/36; G11C29/56; G01R31/3193
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
211 words
A test pattern generator (1) for generating expected value data to carry out logical comparison with an output of a device (2) under test characterized as having: a data register (41) for taking in a data signal from a data generator (13) by a first write signal from a control signal generator (15); an address selector (44) for selecting predetermined bits from an address signal generated by an address generator (12); a mask data register file (42) for storing a data signal from said data generator (13) into an area specified by a data select signal output from said address selector (44) by a second write signal from said control signal generator (15); a write data register file (43) for storing a data signal from said data generator (13) into an area specified by a data select signal output from said address selector (44) by a third write signal from said control signal generator (15); A data formatter (60) which synthesizes and outputs the output data of said data register (41) or the output data of said data generator (13) based on the output signal of said address selector (44), the output signal of said mask data register file (42) and the output signal of said write data register file (43).
Claim 2
Dependent Claim
211 words
A test pattern generator (1) for generating expected value data to carry out logical comparison with an output of a device (2) under test characterized as having: a data register (41) for taking in a data signal from a data generator (13) by a first write signal from a control signal generator (15); an address selector (44) for selecting predetermined bits from an address signal generated by an address generator (12); a mask data register file (42) for storing a data signal from said data generator (13) into an area specified by a data select signal output from said address selector (44) by a second write signal from said control signal generator (15); a write data register file (43) for storing a data signal from said data generator (13) into an area specified by a data select signal output from said address selector (44) by a third write signal from said control signal generator (15); A data formatter (60) which synthesizes and outputs the output data of said data register (41) or the output data of said data generator (13) based on the output signal of said address selector (44), the output signal of said mask data register file (42) and the output signal of said write data register file (43).
Claim 3
Dependent Claim
44 words
A test pattern generator of claim 1 characterized as having: a multiplexer (50) that selects either the output signal of the data formatter (60) or the output signal of the data generator (13) based on the select signal from a control signal generator (15).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-04 | 2002-07-06 | 2003-01-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-04 | 2006-07-06 | 2007-01-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-04 | 2010-07-06 | 2011-01-05 | $7700.00 | Window Closed / Lapsed |