US5852319A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gate electrode for semiconductor device
Assignee: Samsung Electronics Co Ltd
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Filing: 1997-10-17
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Granted: 1998-12-22
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Expires: 2017-10-17
Abstract
Abstract A gate electrode in a semiconductor device comprising; a gate oxide layer formed on a semiconductor substrate, a polysilicon layer formed on the gate oxide layer, a silicide layer formed on the polysilicon layer and, a metal silicide layer formed on the silicide layer.
Inventors
- 👤 Young-sun Kim
- 👤 Nae-in Lee
- 👤 Dae-hong Ko
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:58
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/0131; H10D64/20; H10D64/27; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D64/663; Y; Y10; Y10S; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
93 words
A gate electrode in a semiconductor device, comprising: a gate oxide layer formed on a semiconductor substrate; a polysilicon layer formed on the gate oxide layer; a first silicide layer having a first melting point formed over the polysilicon layer; and a second silicide layer having a second melting point formed between the polysilicon layer and the first silicide layer, to prevent metal particles from contaminating the gate oxide layer and to prevent silicon particles from contaminating the first silicide layer, wherein the second melting point is higher than the first melting point.
Claim 2
Dependent Claim
93 words
A gate electrode in a semiconductor device, comprising: a gate oxide layer formed on a semiconductor substrate; a polysilicon layer formed on the gate oxide layer; a first silicide layer having a first melting point formed over the polysilicon layer; and a second silicide layer having a second melting point formed between the polysilicon layer and the first silicide layer, to prevent metal particles from contaminating the gate oxide layer and to prevent silicon particles from contaminating the first silicide layer, wherein the second melting point is higher than the first melting point.
Claim 3
Dependent Claim
35 words
The gate electrode of claim 1, wherein the second silicide layer comprises one selected from a group consisting of: tungsten silicide (WSi x ), tantalum silicide (TaSi 2 ) and molybdenum silicide (MoSi 2 ).
Claim 4
Dependent Claim
40 words
The gate electrode of claim 1, wherein the first silicide layer comprises one selected from a group consisting of: titanium silicide (TiSi 2 ), tantalum silicide (TaSi 2 ), cobalt silicide (CoSi 2 ), and molybdenum silicide (MoSi 2 ).
Claim 5
Dependent Claim
81 words
A gate electrode in a semiconductor device, comprising: a gate oxide layer formed on a semiconductor substrate; a polysilicon layer formed on the gate oxide layer; a titanium silicide layer formed over the polysilicon layer; and a metal silicide layer having a higher melting point than that of titanium silicide formed between the polysilicon layer and the titanium silicide layer, to prevent titanium particles from contaminating the gate oxide layer and to prevent silicon particles from contaminating the titanium silicide layer.
Claim 6
Dependent Claim
81 words
A gate electrode in a semiconductor device, comprising: a gate oxide layer formed on a semiconductor substrate; a polysilicon layer formed on the gate oxide layer; a titanium silicide layer formed over the polysilicon layer; and a metal silicide layer having a higher melting point than that of titanium silicide formed between the polysilicon layer and the titanium silicide layer, to prevent titanium particles from contaminating the gate oxide layer and to prevent silicon particles from contaminating the titanium silicide layer.
Claim 7
Dependent Claim
34 words
The gate electrode of claim 4, wherein the metal silicide layer comprises one selected from a group consisting of: tungsten silicide (WSi x ), tantalum silicide (TaSi 2 ) molybdenum silicide (MoSi 2 ).
References Cited (Backward Citations)
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JPS61166075A
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JPS63284857A
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JPH02192161A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-21 | 2002-06-22 | 2002-12-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-21 | 2006-06-22 | 2006-12-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-21 | 2010-06-22 | 2010-12-22 | $7700.00 | Window Closed / Lapsed |