Method for numerically scrambling data and its application to a programmable circuit

Claim 2

A programmable circuit, comprising: n input lines and n output lines; n permutation stages, each having a central interconnecting layer which is connected to a respective one of said n output lines and a local interconnecting layer, portions of which connect respective ones of said input lines to the level of said central interconnecting layer; wherein the programming of a permutation stage consists of extending said central interconnecting layer of said permutation stage to a respective local interconnecting layer.

Claim 3

A programmable circuit according to claim 1, wherein said central interconnecting layer and said local interconnecting layer are ion implanted silicon.

Claim 4

A programmable circuit according to claim 1, wherein said central interconnecting layer is made of metal and said local interconnecting layers are ion implanted silicon.

Claim 5

A programmable circuit according to claim 1, wherein a read-only memory is formed and programmed in the same manufacturing steps as said permutation stages.

Claim 6

The circuit of claim 4, wherein the difficulty of visually inspecting a descrambling key is increased by the use of the same manufacturing steps as are used in said read-only memory.

Claim 7

A numerical scrambling method for a programmable circuit, comprising the steps of: (a.) accepting a first set of data from a data bus, applying a first scrambling operation to said first set of data to produce a first set of scrambled data, which is then stored in a first rewritable memory; (b.) accepting a second set of data from said data bus, applying a second scrambling operation, which is different from said first scrambling operation, to said second set of data to produce a second set of scrambled data, which is then stored in a second rewritable memory, which is different from said first rewrittable memory; and (c.) when a memory read request is accepted, reading one of said sets of scrambled data from a respective one of said rewritable memories, applying a respective inverse scrambling operation, corresponding to a respective one of said scrambling operations, to said respective set of scrambled data to reproduce said respective set of data, and placing said set of data on said data bus.

Claim 8

A numerical scrambling method for a programmable circuit, comprising the steps of: (a.) accepting a first set of data from a data bus, applying a first scrambling operation to said first set of data to produce a first set of scrambled data, which is then stored in a first rewritable memory; (b.) accepting a second set of data from said data bus, applying a second scrambling operation, which is different from said first scrambling operation, to said second set of data to produce a second set of scrambled data, which is then stored in a second rewritable memory, which is different from said first rewrittable memory; and (c.) when a memory read request is accepted, reading one of said sets of scrambled data from a respective one of said rewritable memories, applying a respective inverse scrambling operation, corresponding to a respective one of said scrambling operations, to said respective set of scrambled data to reproduce said respective set of data, and placing said set of data on said data bus.

Claim 9

A method according to claim 6, wherein said scrambling operations are a bit permutation of said data.

Claim 10

The programmable system of claim 6, wherein said first rewritable memory is a random access memory.

Claim 11

The programmable system of claim 6, wherein said second rewritable memory is an electrically erasable, programmable memory.

Claim 12

The programmable system of claim 6, wherein said first set of data transmitted on said data bus is scrambled.

Claim 13

The programmable system of claim 6, wherein said second set of data transmitted on said data bus is unscrambled.

Claim 14

The programmable system of claim 6, further comprising a read-only memory in which instructions are stored and transmitted to a data bus in scrambled form.

Claim 15

A method according to claim 6, wherein said scrambling operations are performed by a passive circuit.

Claim 16

A numerical scrambling method for a programmable circuit, comprising the steps of: (a.) generating a first set of data: (b.) applying a first scrambling operation to said first set of data to obtain a second set of scrambled data; (c.) transmitting said second set of scrambled data over a data bus to a rewritable memory, (d.) applying a second scrambling operation to said second set of scrambled data to produce a third set of scrambled data and storing said second set of scrambled data n said rewritable memory; (e.) reading said third set of scrambled data from said rewritable memory and applying an inverse scrambling operation, corresponding to said second scrambling operation, to said third set of scrambled data to reproduce said second set of scrambled data, which is transmitted over said data bus; (f.) applying an inverse scrambling operation, corresponding to said first scrambling operation, to said second set of scrambled data, to reproduce said first set of data.

Claim 17

A numerical scrambling method for a programmable circuit, comprising the steps of: (a.) generating a first set of data: (b.) applying a first scrambling operation to said first set of data to obtain a second set of scrambled data; (c.) transmitting said second set of scrambled data over a data bus to a rewritable memory, (d.) applying a second scrambling operation to said second set of scrambled data to produce a third set of scrambled data and storing said second set of scrambled data n said rewritable memory; (e.) reading said third set of scrambled data from said rewritable memory and applying an inverse scrambling operation, corresponding to said second scrambling operation, to said third set of scrambled data to reproduce said second set of scrambled data, which is transmitted over said data bus; (f.) applying an inverse scrambling operation, corresponding to said first scrambling operation, to said second set of scrambled data, to reproduce said first set of data.

Claim 18

A method according to claim 14, wherein said scrambling operations are a bit permutation of the data to be scrambled.

Claim 19

The method of claim 14, wherein said scrambling operations are performed by a passive circuit.

Claim 20

A memory comprising: a memory; a data bus on which are transmitted a first set of data, which is in a scrambled form; a scrambling circuit having an first and second port, said first port connected to said data bus, said second port being operatively connected to said memory; wherein said scrambling circuit performs a permutation of said first set of data to obtain a second set of data which is then stored in said memory and performs a reverse permutation on said second set of data in said memory to reproduce said first set of data which is then transmitted on said data bus.

Claim 21

A memory comprising: a memory; a data bus on which are transmitted a first set of data, which is in a scrambled form; a scrambling circuit having an first and second port, said first port connected to said data bus, said second port being operatively connected to said memory; wherein said scrambling circuit performs a permutation of said first set of data to obtain a second set of data which is then stored in said memory and performs a reverse permutation on said second set of data in said memory to reproduce said first set of data which is then transmitted on said data bus.

Claim 22

A memory according to claim 17, wherein said memory is rewritable.

Claim 23

A method according to claim 17, wherein said scrambling circuit is a passive circuit.

Claim 24

A processing unit comprising: a processor, connected through a data bus to a first and a second memory; a first passive scrambling circuit having a first and a second port, and connected to receive a first data string from said data bus and to permute said first data string into a first scrambled data set to be stored in said first memory; a second passive scrambling circuit having a first and a second port, and connected to receive a second data string from said data bus and to permute said second data string into a second scrambled data set to be stored in said second memory; wherein said first memory is a different type of memory from said second memory; wherein said first scrambling circuit performs a different permutation from said second scrambling circuit.

Claim 25

A processing unit comprising: a processor, connected through a data bus to a first and a second memory; a first passive scrambling circuit having a first and a second port, and connected to receive a first data string from said data bus and to permute said first data string into a first scrambled data set to be stored in said first memory; a second passive scrambling circuit having a first and a second port, and connected to receive a second data string from said data bus and to permute said second data string into a second scrambled data set to be stored in said second memory; wherein said first memory is a different type of memory from said second memory; wherein said first scrambling circuit performs a different permutation from said second scrambling circuit.

Claim 26

A processing unit according to claim 20, wherein said first and second scrambling circuits are passive logic circuits.

Claim 27

A numerical scrambling method comprising the steps of: reading data from a memory address: and applying a scrambling operation to at least two bits of said data to produce scrambled data, wherein said scrambling operation is performed by a passive circuit, said passive circuit comprising: n input lines; n output lines; and a connection from each said input line to a respective output line such that data received on said input lines is output on said output lines in at least partially scrambled form, wherein the pattern of metallization, including used and unused vias, increases the difficulty of visually inspecting a descrambling key.

Claim 28

A numerical scrambling method comprising the steps of: reading data from a memory address: and applying a scrambling operation to at least two bits of said data to produce scrambled data, wherein said scrambling operation is performed by a passive circuit, said passive circuit comprising: n input lines; n output lines; and a connection from each said input line to a respective output line such that data received on said input lines is output on said output lines in at least partially scrambled form, wherein the pattern of metallization, including used and unused vias, increases the difficulty of visually inspecting a descrambling key.

Claim 31

The method of claim 23, wherein said passive descrambling unit comprises: n input lines; n output lines; a connection from each said input line to a respective output line such that data received on said input lines is output on said output lines in at least a partially scrambled form; wherein the pattern of metallization patterns, including used and unused vias, increases the difficulty of visually inspecting a descrambling key.