US5850150A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Final stage clock buffer in a clock distribution network
Assignee: Oracle America Inc
•
Filing: 1996-05-01
•
Granted: 1998-12-15
•
Expires: 2016-05-01
Abstract
Abstract A final stage clock buffer for use in a clock distribution network in a circuit with scan design includes a demultiplexer circuit and a control circuit. The buffer receives an input clock signal and outputs a clock signal and a scan clock signal. The buffer can operate in a functional mode, a scan mode and a hold mode. The demultiplexer circuit receives the input clock signal and a scan enable signal. The scan enable signal, when asserted, causes the buffer to enter the scan mode. In the scan mode, the demultiplexer circuit propagates the input clock signal to a scan clock terminal and a constant logic level to a clock terminal. When the scan enable signal is deasserted, the demultiplexer circuit propagates the input clock signal to the clock terminal and a constant logic level to the scan clock terminal. The control circuit receives a chip-enable signal. When the chip-enable signal is asserted while the scan signal is deasserted, the buffer enters the functional mode. The asserted chip-enable signal causes the control circuit to allow the input clock signal to continue to propagate to the clock terminal. When both the chip-enable signal and the scan signal are deasserted, the buffer enters the hold mode. The deasserted chip-enable signal causes the control circuit to stop the propagation of the input clock signal to the clock output terminal and, instead, causes the clock signal to remain in a constant logic state.
Inventors
- 👤 Sundari S. Mitra
- 👤 Prasad H. Chalasani
- 👤 Marc Elliot Levitt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:51
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318552; G01R31/318541
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
217 words
A clock signal buffer circuit comprising: a first input terminal configured to receive a clock input signal; a second input terminal configured to receive a select signal; a third input terminal configured to receive an enable signal; a first output terminal; a second output terminal; a demultiplexer circuit having a first output lead coupled to said first output terminal, a second output lead coupled to said second output terminal, a first input lead coupled to said first input terminal and a second input lead coupled to said second input terminal, wherein said demultiplexer circuit is operative to provide a clock output signal dependent on said clock input signal to said first output lead in response to said select signal being in a first state and to provide a scan output signal to said second output lead in response to said select signal being in a second state; and a control circuit coupled to said demultiplexer and having a control input lead coupled to said third input terminal and an output lead coupled to said first output terminal, wherein, in response to said enable signal being in a first state, said control circuit is operative to provide to said output lead of said control circuit an output signal dependent on said clock output signal of said demultiplexer circuit.
Claim 2
Dependent Claim
217 words
A clock signal buffer circuit comprising: a first input terminal configured to receive a clock input signal; a second input terminal configured to receive a select signal; a third input terminal configured to receive an enable signal; a first output terminal; a second output terminal; a demultiplexer circuit having a first output lead coupled to said first output terminal, a second output lead coupled to said second output terminal, a first input lead coupled to said first input terminal and a second input lead coupled to said second input terminal, wherein said demultiplexer circuit is operative to provide a clock output signal dependent on said clock input signal to said first output lead in response to said select signal being in a first state and to provide a scan output signal to said second output lead in response to said select signal being in a second state; and a control circuit coupled to said demultiplexer and having a control input lead coupled to said third input terminal and an output lead coupled to said first output terminal, wherein, in response to said enable signal being in a first state, said control circuit is operative to provide to said output lead of said control circuit an output signal dependent on said clock output signal of said demultiplexer circuit.
Claim 3
Dependent Claim
46 words
The buffer circuit of claim 1 wherein, in response to said select signal being in said first state, said demultiplexer circuit is operative to cause said scan clock output signal on said second output lead of said demultiplexer circuit to be in a substantially constant state.
Claim 4
Dependent Claim
45 words
The buffer circuit of claim 1 wherein, in response to said select signal being in said second state, said demultiplexer circuit is operative to cause said clock output signal on said first output lead of said demultiplexer circuit to be in a substantially constant state.
Claim 5
Dependent Claim
44 words
The buffer circuit of claim 1 wherein, in response to said enable signal being in a second state, said control circuit is operative to cause said output signal on said output lead of said control circuit to be in a substantially constant first state.
Claim 6
Dependent Claim
26 words
The buffer circuit of claim 4 wherein said first output lead of said demultiplexer circuit is coupled to said first output terminal through said control circuit.
Claim 7
Dependent Claim
44 words
The buffer circuit of claim 5 wherein, in response to said select signal being in said second state, said control circuit is operative to cause said output signal on said output lead of said control circuit to be in a substantially constant second state.
Claim 8
Dependent Claim
52 words
The buffer circuit of claim 6 wherein, in response to said signal being in said second state and said enable signal being in said second state, said control circuit is operative to cause said output signal on said output lead of said control circuit to be in said substantially constant second state.
Claim 9
Dependent Claim
38 words
The buffer circuit of claim 7 further comprising a differential driver circuit coupled to said output lead of said control circuit, said differential driver circuit coupling said output lead of said control circuit to said first output terminal.
Claim 10
Dependent Claim
40 words
The buffer circuit of claim 1 further comprising a differential driver circuit coupled to said second output lead of said demultiplexer circuit, said differential driver circuit coupling said second output lead of said demultiplexer circuit to said second output terminal.
Claim 11
Dependent Claim
244 words
A clock signal buffer circuit having first, second and third modes of operation, said buffer circuit comprising: a first input terminal configured to receive a clock input signal, a second input terminal configured to receive a select signal; a third input terminal configured to receive an enable signal; a first output terminal; a second output terminal; a demultiplexer circuit having a first output lead coupled to said first output terminal, a second output lead coupled to said second output terminal, a first input lead coupled to said first input terminal and a second input lead coupled to said second input terminal; and a control circuit coupled to said demultiplexer and having a control input lead coupled to said third input terminal and an output lead coupled to said first output terminal, wherein said buffer circuit is configured to provide a clock output signal at said first output terminal and a scan clock output signal at said second output terminal, said buffer circuit being selectably configured into said first, second and third modes in response to said enable and select signals, and wherein (a) in said first mode, said clock signal is dependent on said clock input signal, (b) in said second mode, said scan clock output signal is dependent on said clock output signal, and (c) in said third mode, said clock output signal is held in a substantially constant state and said scan clock output signal is held at a substantially constant state.
Claim 12
Dependent Claim
244 words
A clock signal buffer circuit having first, second and third modes of operation, said buffer circuit comprising: a first input terminal configured to receive a clock input signal, a second input terminal configured to receive a select signal; a third input terminal configured to receive an enable signal; a first output terminal; a second output terminal; a demultiplexer circuit having a first output lead coupled to said first output terminal, a second output lead coupled to said second output terminal, a first input lead coupled to said first input terminal and a second input lead coupled to said second input terminal; and a control circuit coupled to said demultiplexer and having a control input lead coupled to said third input terminal and an output lead coupled to said first output terminal, wherein said buffer circuit is configured to provide a clock output signal at said first output terminal and a scan clock output signal at said second output terminal, said buffer circuit being selectably configured into said first, second and third modes in response to said enable and select signals, and wherein (a) in said first mode, said clock signal is dependent on said clock input signal, (b) in said second mode, said scan clock output signal is dependent on said clock output signal, and (c) in said third mode, said clock output signal is held in a substantially constant state and said scan clock output signal is held at a substantially constant state.
Claim 13
Dependent Claim
25 words
The buffer circuit of claim 10 wherein said buffer circuit is configured into said second state when said second input is in a first state.
Claim 14
Dependent Claim
33 words
The buffer circuit of claim 10 wherein said buffer is configured into said first mode when said select signal is in a second state and said enable signal is in a first state.
Claim 15
Dependent Claim
33 words
The buffer circuit of claim 10 wherein said buffer is configured into said third mode when said select signal is in said second state and said enable signal is in a second state.
Claim 16
Dependent Claim
69 words
The buffer circuit of claim 10 wherein said demultiplexer circuit comprises: a first NAND gate having a first input lead coupled to said first input terminal and having a second input lead coupled to receive said select signal; and a second NAND gate having a first input lead coupled to said first input terminal and having a second input lead coupled to receive a complement of said select signal.
Claim 17
Dependent Claim
270 words
A computer system comprising: a memory; an interface capable of interacting with a peripheral device; and a circuit coupled to said memory and said interface, said circuit including a clock signal buffer circuit having first, second and third modes of operation, said buffer circuit comprising: a first input terminal configured to receive a clock input signal; a second input terminal configured to receive a select signal; a third input terminal configured to receive a enable signal; a first output terminal; a second output terminal; a demultiplexer circuit having a first output lead coupled to said first output terminal, a second output lead coupled to said second output terminal, a first input lead coupled to said first input terminal and a second input lead coupled to said second input terminal; and a control circuit coupled to said demultiplexer and having a control input lead coupled to said third input terminal and an output lead coupled to said first output terminal, wherein said buffer circuit provides a clock output signal at said first output terminal and a scan clock output signal at said second output terminal, said buffer circuit being selectable configured into said first, second and third modes in response to said enable and select signals, and wherein, (a) in said first mode, said clock output signal is dependent on said clock input signal, (b) in said second mode, said scan clock output signal is dependent on said clock output signal, and (c) in said third mode, said clock output signal is held in a substantially constant state and said scan clock output signal is held at a substantially constant state.
Claim 18
Dependent Claim
270 words
A computer system comprising: a memory; an interface capable of interacting with a peripheral device; and a circuit coupled to said memory and said interface, said circuit including a clock signal buffer circuit having first, second and third modes of operation, said buffer circuit comprising: a first input terminal configured to receive a clock input signal; a second input terminal configured to receive a select signal; a third input terminal configured to receive a enable signal; a first output terminal; a second output terminal; a demultiplexer circuit having a first output lead coupled to said first output terminal, a second output lead coupled to said second output terminal, a first input lead coupled to said first input terminal and a second input lead coupled to said second input terminal; and a control circuit coupled to said demultiplexer and having a control input lead coupled to said third input terminal and an output lead coupled to said first output terminal, wherein said buffer circuit provides a clock output signal at said first output terminal and a scan clock output signal at said second output terminal, said buffer circuit being selectable configured into said first, second and third modes in response to said enable and select signals, and wherein, (a) in said first mode, said clock output signal is dependent on said clock input signal, (b) in said second mode, said scan clock output signal is dependent on said clock output signal, and (c) in said third mode, said clock output signal is held in a substantially constant state and said scan clock output signal is held at a substantially constant state.
Claim 19
Dependent Claim
25 words
The computer system of claim 15 wherein said buffer circuit is configured into said second state when said second input is in a first state.
Claim 20
Dependent Claim
34 words
The computer system of claim 15 wherein said buffer circuit is configured into said first mode when said select signal is in a second state and said enable signal is in a first state.
Claim 21
Dependent Claim
34 words
The computer system of claim 15 wherein said buffer circuit is configured into said third mode when said select signal is in said second state and said enable signal is in a second state.
Claim 22
Dependent Claim
243 words
A computer system comprising: a memory; an interface capable of interacting with a peripheral device; and a circuit coupled to said memory and said interface, said circuit including a buffer circuit comprising: a first input terminal configured to receive a clock input signal; a second input terminal configured to receive a select signal; a third input terminal configured to receive a enable signal; a first output terminal; a second output terminal; a demultiplexer circuit having a first output lead coupled to said first output terminal, a second output lead coupled to said second output, terminal, a first input lead coupled to said first input terminal and a second input lead coupled to said second input terminal, wherein said demultiplexer circuit is operative to provide a clock output signal dependent on said clock input signal to said first output lead in response to said select signal being in a first state and to provide a scan clock output signal to said second output lead in response to said signal being in a second state; and a control circuit coupled to said demultiplexer and having a control input lead coupled to said third input terminal and an output lead coupled to said first output terminal, wherein, in response to said enable signal being in a first state, said control circuit is operative to provide to said output lead of said control circuit an output signal dependent on said clock output signal of said demultiplexer circuit.
Claim 23
Dependent Claim
243 words
A computer system comprising: a memory; an interface capable of interacting with a peripheral device; and a circuit coupled to said memory and said interface, said circuit including a buffer circuit comprising: a first input terminal configured to receive a clock input signal; a second input terminal configured to receive a select signal; a third input terminal configured to receive a enable signal; a first output terminal; a second output terminal; a demultiplexer circuit having a first output lead coupled to said first output terminal, a second output lead coupled to said second output, terminal, a first input lead coupled to said first input terminal and a second input lead coupled to said second input terminal, wherein said demultiplexer circuit is operative to provide a clock output signal dependent on said clock input signal to said first output lead in response to said select signal being in a first state and to provide a scan clock output signal to said second output lead in response to said signal being in a second state; and a control circuit coupled to said demultiplexer and having a control input lead coupled to said third input terminal and an output lead coupled to said first output terminal, wherein, in response to said enable signal being in a first state, said control circuit is operative to provide to said output lead of said control circuit an output signal dependent on said clock output signal of said demultiplexer circuit.
Claim 24
Dependent Claim
46 words
The computer system of claim 19 wherein, in response to said select signal being in said first state, said demultiplexer circuit is operative to cause said scan clock output signal on said second output lead of said demultiplexer circuit to be in a substantially constant state.
Claim 25
Dependent Claim
45 words
The computer system of claim 19 wherein, in response to said select signal being in said second state, said demultiplexer circuit is operative to cause said clock output signal on said first output lead of said demultiplexer circuit to be in a substantially constant state.
Claim 26
Dependent Claim
44 words
The computer system of claim 19 wherein, in response to said enable signal being in a second state, said control circuit is operative to cause said output signal on said output lead of said control circuit to be in a substantially constant first state.
Claim 27
Dependent Claim
26 words
The computer system of claim 22 wherein said first output lead of said demultiplexer circuit is coupled to said first output terminal through said control circuit.
Claim 28
Dependent Claim
44 words
The computer system of claim 23 wherein, in response to said select signal being in said second state, said control circuit is operative to cause said output signal on said output lead of said control circuit to be in a substantially constant second state.
Claim 29
Dependent Claim
53 words
The computer system of claim 24 wherein, in response to said select signal being in said second state and said enable signal being in said second state, said control circuit is operative to cause said output signal on said output lead of said control circuit to be in said substantially constant second state.
Claim 30
Dependent Claim
38 words
The computer system of claim 25 further comprising a differential driver circuit coupled to said output lead of said control circuit, said differential driver circuit coupling said output lead of said control circuit to said first output terminal.
Claim 31
Dependent Claim
39 words
The computer system of claim 19 further comprising a differential driver circuit coupled to said output lead of said demultiplexer circuit, said differential driver circuit coupling said second output lead of said demultiplexer circuit to said second output terminal.
References Cited (Backward Citations)
US5109353A
Cited
US5497109A
Cited
US5235521A
Cited
US5220217A
Cited
US5396129A
Cited
US5489857A
Cited
US5586307A
Cited
US5481209A
Cited
US5570045A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-14 | 2002-06-15 | 2002-12-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-14 | 2006-06-15 | 2006-12-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-14 | 2010-06-15 | 2010-12-15 | $7700.00 | Window Closed / Lapsed |