US5848434A
Expired / Lapsed
US
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Method and apparatus for caching state information within a directory-based coherency memory system
Assignee: Intel Corp
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Filing: 1996-12-09
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Granted: 1998-12-08
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Expires: 2016-12-09
Abstract
Abstract A directory-based cache coherency memory system for a multiprocessor computer system. The memory system includes a system memory shared by the multiple processors within the computer system; a plurality of data cache memories, at least one data cache memory associated with each processor; a system of busses interconnecting the system memory with the plurality of data cache memories and processors, and a state cache memory associated with the shared system memory for the storage of memory line state information identifying where within the system memory and the plurality of data cache memories the most current copy of a line of memory resides. The state cache memory is sized to store state information for only a portion of the memory lines included in system memory, e.g., one sixteenth of the memory lines contained in system memory, in recognition that rarely will all of system memory be utilized (cached) at any one time. The state cache can be a direct mapped cache wherein state information for an associated line of memory is stored within the state cache together with a tag field being a first portion of the address of the associated line of memory, and indexed within the state cache by the remaining portion of the address.
Inventors
- 👤 Gene F. Young
- 👤 Roy M. Stevens
- 👤 Larry C. James
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:58
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0817; G06F12/0826; G06F12/0813; G06F12/082
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
178 words
A centralized/distributed directory-based cache coherency memory system for a computer system including multiple processors, the memory system comprising: a system memory shared by said multiple processors; a plurality of data cache memories, at least one data cache memory associated with each one of said processors; a processor line status table (PLST) associated with each of said data cache memories, said PLST comprising Modified-Exclusive-Shared-Invalid (MESI) state bits; a system of busses interconnecting said system memory with said plurality of data cache memories and said multiple processors; and a state cache memory associated with said shared system memory and connected to said system of busses for the storage of a memory line status table (MLST), said MLST to store memory line state information identifying where within said plurality of data cache memories a copy of a line of system memory potentially resides, said memory line state information comprising not cached, shared, and owned state bits, wherein the PLST associated with each of the identified data cache memories indicates local state information for the copy of the line of system memory.
Claim 2
Dependent Claim
178 words
A centralized/distributed directory-based cache coherency memory system for a computer system including multiple processors, the memory system comprising: a system memory shared by said multiple processors; a plurality of data cache memories, at least one data cache memory associated with each one of said processors; a processor line status table (PLST) associated with each of said data cache memories, said PLST comprising Modified-Exclusive-Shared-Invalid (MESI) state bits; a system of busses interconnecting said system memory with said plurality of data cache memories and said multiple processors; and a state cache memory associated with said shared system memory and connected to said system of busses for the storage of a memory line status table (MLST), said MLST to store memory line state information identifying where within said plurality of data cache memories a copy of a line of system memory potentially resides, said memory line state information comprising not cached, shared, and owned state bits, wherein the PLST associated with each of the identified data cache memories indicates local state information for the copy of the line of system memory.
Claim 3
Dependent Claim
34 words
The memory system in accordance with claim 1, wherein: said state cache memory has a size capable of storing state information for a fraction of the lines of memory contained within said system memory.
Claim 4
Dependent Claim
34 words
The memory system in accordance with claim 1, wherein: said state cache memory has a size capable of storing state information for one sixteenth of the lines of memory contained within said system memory.
Claim 5
Dependent Claim
19 words
The memory system in accordance with claim 1, wherein: said state cache memory is a direct mapped cache memory.
Claim 6
Dependent Claim
169 words
A multiprocessor computer system comprising: a plurality of processors; a plurality of data cache memories, at least one data cache memory associated with each one of said processors; a processor line status table (PLST) associated with each of said data cache memories said PLST comprising Modified-Exclusive-Shared-Invalid (MESI) state bits; a system memory shared by said multiple processors; a system of busses interconnecting said system memory with said plurality of data cache memories and said multiple processors; and a state cache memory associated with said shared system memory and connected to said system of busses for the storage of a memory line status table (MLST), said MLST to store memory line state information identifying where within said plurality of data cache memories a copy of a line of system memory potentially resides, said memory line state information comprising not cached, share and owned state bits, wherein the PLST associated with each of the identified data cache memories indicates local state information for the copy of the line of system memory.
Claim 7
Dependent Claim
169 words
A multiprocessor computer system comprising: a plurality of processors; a plurality of data cache memories, at least one data cache memory associated with each one of said processors; a processor line status table (PLST) associated with each of said data cache memories said PLST comprising Modified-Exclusive-Shared-Invalid (MESI) state bits; a system memory shared by said multiple processors; a system of busses interconnecting said system memory with said plurality of data cache memories and said multiple processors; and a state cache memory associated with said shared system memory and connected to said system of busses for the storage of a memory line status table (MLST), said MLST to store memory line state information identifying where within said plurality of data cache memories a copy of a line of system memory potentially resides, said memory line state information comprising not cached, share and owned state bits, wherein the PLST associated with each of the identified data cache memories indicates local state information for the copy of the line of system memory.
Claim 8
Dependent Claim
34 words
The computer system in accordance with claim 5, wherein: said state cache memory has a size capable of storing state information for a fraction of the lines of memory contained within said system memory.
Claim 9
Dependent Claim
34 words
The computer system in accordance with claim 5, wherein: said state cache memory has a size capable of storing state information for one sixteenth of the lines of memory contained within said system memory.
Claim 10
Dependent Claim
19 words
The memory system in accordance with claim 5, wherein: said state cache memory is a direct mapped cache memory.
Claim 11
Dependent Claim
211 words
A multiprocessor computer system, comprising: a plurality of processors; a plurality of data cache memories, at least one data cache memory associated with each one of said processors; a system memory shared by said multiple processors; first and second memory busses connecting said system memory with said plurality of data cache memories and said multiple processors; and a centralized/distributed directory-based cache coherency system comprising: a Processor Line Status Table (PLST) associated with each data cache memory, each PLST containing state information indicating whether a line of memory within the PLST contains a valid copy of a line of memory within said shared system memory, said PLST comprising Modified-Exclusive-Shared-Invalid (MESI) state bits; and a state cache memory associated with said shared system memory and connected to said system of busses for the storage of a memory line status table (MLST), said MLST to store memory line state information identifying one of which data cache memories, if any, potentially contain the valid copy of said line of shared system memory, and which of the first and second memory busses, if any, are connected to data cache memories which potentially contain the valid copy of said line of shared system memory, said memory line state information comprising not cached, shared, and owned state bits.
Claim 12
Dependent Claim
211 words
A multiprocessor computer system, comprising: a plurality of processors; a plurality of data cache memories, at least one data cache memory associated with each one of said processors; a system memory shared by said multiple processors; first and second memory busses connecting said system memory with said plurality of data cache memories and said multiple processors; and a centralized/distributed directory-based cache coherency system comprising: a Processor Line Status Table (PLST) associated with each data cache memory, each PLST containing state information indicating whether a line of memory within the PLST contains a valid copy of a line of memory within said shared system memory, said PLST comprising Modified-Exclusive-Shared-Invalid (MESI) state bits; and a state cache memory associated with said shared system memory and connected to said system of busses for the storage of a memory line status table (MLST), said MLST to store memory line state information identifying one of which data cache memories, if any, potentially contain the valid copy of said line of shared system memory, and which of the first and second memory busses, if any, are connected to data cache memories which potentially contain the valid copy of said line of shared system memory, said memory line state information comprising not cached, shared, and owned state bits.
Claim 13
Dependent Claim
181 words
In a computer system including a shared system memory, a plurality of data cache memories, and a system of busses interconnecting said system memory with said plurality of data cache memories, a method for maintaining consistency between data residing in said shared system memory and said plurality of data cache memories, said method comprising the steps of: providing a state cache memory connected to said system of busses and a processor line status table (PLST) associated with each of the data cache memories, said state cache memory being associated with said system memory and addressed concurrently with said system memory; and caching a memory line status table (MLST), said MLST to store memory line state information identifying where within said plurality of data cache memories a copy of a line of system memory potentially resides, wherein said PLST associated with each of the identified data cache memories indicates local state information for the copy of the line of system memory, said PLST comprising Modified-Exclusive-Shared-Invalid (MESI) state bits, and said memory line state information comprising not cached, shared and owned state bits.
Claim 14
Dependent Claim
181 words
In a computer system including a shared system memory, a plurality of data cache memories, and a system of busses interconnecting said system memory with said plurality of data cache memories, a method for maintaining consistency between data residing in said shared system memory and said plurality of data cache memories, said method comprising the steps of: providing a state cache memory connected to said system of busses and a processor line status table (PLST) associated with each of the data cache memories, said state cache memory being associated with said system memory and addressed concurrently with said system memory; and caching a memory line status table (MLST), said MLST to store memory line state information identifying where within said plurality of data cache memories a copy of a line of system memory potentially resides, wherein said PLST associated with each of the identified data cache memories indicates local state information for the copy of the line of system memory, said PLST comprising Modified-Exclusive-Shared-Invalid (MESI) state bits, and said memory line state information comprising not cached, shared and owned state bits.
Claim 15
Dependent Claim
33 words
The method in accordance with claim 10, wherein: said state cache memory has a size capable of storing state information for a fraction of the lines of memory contained within said system memory.
Claim 16
Dependent Claim
34 words
The method system in accordance with claim 10, wherein: said state cache memory has a size capable of storing state information for one sixteenth of the lines of memory contained within said system memory.
Claim 17
Dependent Claim
19 words
The method system in accordance with claim 10, wherein: said state cache memory is a direct mapped cache memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-07 | 2002-06-08 | 2002-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-07 | 2006-06-08 | 2006-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-07 | 2010-06-08 | 2010-12-08 | $7700.00 | Window Closed / Lapsed |